From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Implementation And Verification Of A Lunar Mission Subsystems (II)

El presente trabajo final de carrera consiste en implementar y verificar algunos de los subsistemas que forman la misión Lunar diseñada por el equipo Team FREDNET con motivo del Google Lunar X Prize. Uno de los proyectistas se encargará de los subsistemas del Rover Lunar y el otro se encargará de los subsistemas del Lunar Lander. Debido a que hay multiples subsistemas es posible que haya un tercer proyectista. Este proyecto se realiza en colaboración con otros investigadores de múltiples nacionalidades por lo que requiere formar parte del grupo en un proyecto real de exploración lunar. Este proyecto incluye habilidades de trabajo en equipo, preparación de resultados, toma de decisiones, etc. REQUISITOS: - Estar terminando la carrera técnica de Sistemas, Telemática o Aeronáutica (Obligatorio) - Disponibilidad horaria y presencial (Obligatorio) - Tener conocimientos en buses y radio-enlaces (Deseable) - Manejo de sistema operativo WINDOWS y LINUX (Deseable

Model-Based Development of Distributed Embedded Systems by the Example of the Scicos/SynDEx Framework

The embedded systems engineering industry faces increasing demands for more functionality, rapidly evolving components, and shrinking schedules. Abilities to quickly adapt to changes, develop products with safe design, minimize project costs, and deliver timely are needed. Model-based development (MBD) follows a separation of concerns by abstracting systems with an appropriate intensity. MBD promises higher comprehension by modeling on several abstraction-levels, formal verification, and automated code generation. This thesis demonstrates MBD with the Scicos/SynDEx framework on a distributed embedded system. Scicos is a modeling and simulation environment for hybrid systems. SynDEx is a rapid prototyping integrated development environment for distributed systems. Performed examples implement well-known control algorithms on a target system containing several networked microcontrollers, sensors, and actuators. The addressed research question tackles the feasibility of MBD for medium-sized embedded systems. In the case of single-processor applications experiments show that the comforts of tool-provided simulation, verification, and code-generation have to be weighed against an additional memory consumption in dynamic and static memory compared to a hand-written approach. Establishing a near-seamless modeling-framework with Scicos/SynDEx is expensive. An increased development effort indicates a high price for developing single applications, but might pay off for product families. A further drawback was that the distributed code generated with SynDEx could not be adapted to microcontrollers without a significant alteration of the scheduling tables. The Scicos/SynDEx framework forms a valuable tool set that, however, still needs many improvements. Therefore, its usage is only recommended for experimental purposes.Comment: 146 pages, Master's Thesi

A Multi-layer Fpga Framework Supporting Autonomous Runtime Partial Reconfiguration

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead