The Multiple Gate Mos-Jfet

A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented

Comparison of Three Dimensional Partially and Fully Depleted SOI MOSFET Characteristics Using Mathcad

In this Paper, comparison of three Dimensional characteristics between partially and fully depleted Silicon-On-Insulator (SOI MOSFET) is presented, this is done through 3D device modeling using mathcad, based on the numerical solution of three dimensional Poisson’s equation. Behavior of Various Parameters like Surface Potential, Threshold Voltage, Electric field and Drain current are presented in this paper

Electronics and Sensor Study with the OKI SOI process

While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented

PDSOI and Radiation Effects: An Overview

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling

Investigations on the vulnerability of advanced CMOS technologies to MGy dose environments

This paper investigates the TID sensitivity of silicon-based technologies at several MGy irradiation doses to evaluate their potential for high TID-hardened circuits. Such circuits will be used in several specific applications suc as safety systems of current or future nuclear power plants considering various radiation environments including normal and accidental operating conditions, high energy physics instruments, fusion experiments or deep space missions. Various device designs implemented in well established bulk silicon and Partially Depleted SOI technologies are studied here up to 3 MGy. Furthermore, new insights are given on the vulnerability of more advanced technologies including planar Fully Depleted SOI and multiple-gate SOI transistors at such high dose. Potential of tested technologies are compared and discussed for stand-alone integrated circuits

New approach for SOI pixel sensor:analysis and implementation

Silicon on Insulator (SOI) is an interesting alternative to bulk silicon for the fabrication of integrated circuits due to its advantages with respect to the junction leakage, low switching noise coupling, high temperature immunity, low voltage and low power applications. Recently, SOI transistors have also been used in high speed CPU's due to their high switching performances and their reduced power consumption. Another application where high performances and even higher densities are needed are dynamic memories (DRAM) where floating body SOI MOSFETS were used as an 1T memory node. Using the floating body as a charge storage reduces the unit cell size and drastically increases the bit density and the storage capacity. However, despite technical advances in SOI technology, it has rarely been exploited in optical sensing and imagery. The main reasons are the expected low optical conversion efficiency due to the relatively thin silicon film thicknesses, well below 1 µm and the slow time constants due to slow recombinations at the junctions. In addition, the slim active region reduces the optical bandwidth of such sensors as longer wavelengths are absorbed deeper (and in the case of SOI probably in the buried oxide layer). Despite these major handicaps, it was shown recently that an SOI MOSFET based phototransistor could detect light intensities as low as 5 mW/m2. However, previous work addressed only low light intensities neglecting the slow transients drawbacks. Moreover, as for most fully and partially depleted SOI MOSFET's based photodetectors, it is the drain current variation due to light absorption that was used as a measure of photon densities (for instance the 5 mW/m2 generates 50 fA of photocurrent). Such variations are hard to measure with the needed resolution as such currents are close to the noise levels of any amplifier. This research project proposes a new measurement technique that does not rely on direct quantification of the photocurrent and hence overcomes the problems inherent to noise and low current variations. In addition to that, this novel technique solves the problem of slow drain current recovery time inherent to the slow recombinations at the junctions. This technique relies on the transient charge pumping used to remove continuously photogenerated charges from the electrically insulated body of the MOSFET. Then, since the transistor is always maintained in equilibrium conditions, this approach will get rid of any transient effect occurring in the partially depleted SOI MOSFET. Also presented in this work is an extension of this technique to any floating body MOSFET. We presented also measurement of bulk P-MOSFET whose n-well was left floating and showed that the behaviour was similar to that of a floating body SOI MOSFET. Still using the transient charge pumping to remove extra charge from the floating n-well. Finally, An SOI circuit implementation of this technique was presented. This circuit takes advantage of some of the properties of the floating body SOI MOSFET to implement a first order delta sigma modulator at the pixel level without substantially reducing the fill factor. The first order delta sigma modulator in each pixel, can improve the resolution and offer a direct digital output without the need of an ADC