Throughput-driven floorplanning with wire pipelining

The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires

Characterization and Scaling of MOS Flip Flop Performance in Synchronizer Applications

The measured and calculated values of t he Flip Flop parameters needed to specify synchronizer reliability are presented for 3 different depletion-load, silicon gate, NMOS, R-S Flip Flop circuits with gate lengths ranging from 6μm to 4.2μm. Estimates of the probability of synchronizer failure to resolve within allowed or desired times can be determined from these parameters

Timing models for high-level synthesis

In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Universal Spin-Flip Transition in Itinerant Antiferromagnets

We report a universal spin flip (SF) transition as a function of temperature in spin-density-wave (SDW) systems. At low temperatures the antiferromagnetic (AFM) polarization is parallel to the applied field and above a critical temperature the AFM polarization {\it flips} perpendicular to the field. This transition occurs in {\it any} SDW system and may be considered as a qualitative probe of the itinerant character of AFM in a given material. Our SF transition resolves the longstanding puzzle of the SF transition observed in cromium and may be at the origin of the equally puzzling SDW-I to SDW-II transition in Bechgaard salts for which we make experimental predictions