RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Design Of A 2.4 Ghz Low Power Lc Vco In Umc 0.18u Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Bu çalışmada, Bluetooth uygulamalarında kullanılmak üzere 2.45GHz merkez frekansında çalışan, frekans ayarlaması 2.2GHz ile 2.7GHz arasında değişen, düşük güç (2mW) tüketimi sağlayan bir LC GKO (VCO) tasarlanmıştır. Faz gürültüsünü minimize etmek maksadıyla 4 bit anahtarlamalı IMOS dizisinden yararlanılmıştır. Ayrıca frekansın ince ayarı için kapasite kuplajlı diyot varaktör devresi eklenmiştir. Bu frekans ayarlama tekniğinin faz gürültüsüne etkisi en kötü hal için 50kHz ofsette yaklaşık olarak 2dBc/Hz olup yüksek ofsetlerde yok denecek kadar azdır. Devrenin kaba kontrol gerilimleri 1.4V ve 0V olup, ince ayar gerilimi ise 0.5V ile 1.4V arasındadır. Besleme geriliminin 1.4V olduğu dikkate alındığında devre yüksek entegrasyon olanağı sunmaktadır. Faz gürültüsü 50kHz ofsette -88.6dBc/Hz ile -94.36dBc/Hz arasında olup 3MHz ofsette ise -128.3dBc/Hz ile -130.5dBc/Hz değerlerine ulaşmaktadır.Bu devreye ek olarak daha düşük gerilimli farklı topolojiler aynı akım akıtacak şekilde tasarlanmış ve tezin aynı zamanda ISM bandında çalışan düşük güç sarfiyatı isteyen uygulamalarda gerekli olacak bir GKO ihtiyacı için karşılaştırmalı bir çalışma olması sağlanmıştır.In this study, a low power LC VCO which operates at a center frequency of 2.45GHz over the range between 2.2GHz and 2.7GHz is designed for Bluetooth applications. The oscillator consumes 2mW at a supply voltage of 1.4V. To minimize the phase noise generated by the varactor through AM-PM conversion, 4bits SCA varactor is implemented by employing IMOS varactors. For fine tuning of frequency, a capacitor coupled diode varactor structure is designed. The effect of this overall varactor structure on the phase noise is around 2dBc/Hz at 50kHz offset for the worst case whereas it is negligble at high offsets. The coarse control tuning voltage values are 0V and 1.4V and the fine tuning control voltage varies from 0.5V to 1.4V. Hence, a high integration is achieved by keeping the external voltage at power supply voltage. The phase noise is between -88.6dBc/Hz and -94.36dBc/Hz at 50kHz offset, and between -128.3dBc/Hz and -130.5dBc/Hz at 3MHz offset. In addition to this, several circuits enabling lower supply voltage are simulated by keeping the same current in order to constitute a comparative study for low power applications which do not require stringent phase noise specification at 2.4GHz.Yüksek LisansM.Sc

A Wideband Quadrature VCO Using a Novel Tail Current-Clipping Technique

This thesis presents a Quadrature VCO (QVCO) architecture using a novel tail current-clipping technique that improves the phase noise performance of a traditional QVCO by about 4 dB while obtaining a tuning range of about 4 to 5 GHz. This work introduces an innovative idea based on a new approach of implementing a QVCO without an explicit conventional parallel or series coupling network and eliminates some of the issues associated with a traditional QVCO such as bimodal oscillations and phase noise degradation due to the coupling network. The proposed structure has a lot of advantages over the traditional P-QVCO in terms of both phase noise and power consumption. The proposed QVCO was fabricated in the 40 nm CMOS technology. The measured phase noise at 4.9 GHz was about -123.2 dBc/Hz at 1 MHz offset frequency while the quadrature error was less than 3° over the complete tuning range. The proposed architecture consumes a power of about 7.5 mW from a supply of 1.1 V with a figure-of-merit (FoM) of 188.27 dBc/Hz at 4.9 GHz output frequency

Low-Frequency Noise Phenomena in Switched MOSFETs

In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applie

Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

The Bias Dependence of CMOS 1/F Noise Statistics, its Modeling and Impact on RF Circuits

In the last decade, wireless network routers, multi-media devices with Bluetooth© or similar communication capabilities, mobile cell-phones, and other “RF” devices have found widespread use in the consumer market. The integration and cost advantages of CMOS-only chips have attracted circuit designers in academia and industry, and CMOS technology is now a strong contender along with BiCMOS, and III-V semiconductors for analog / mixed signal and radio frequency applications. RF CMOS technology has numerous advantages that come with the feasibility of system-on-chip. These advantages include reduced fabrication cost and reduced pin count due to die sharing between analog and digital portions. Perhaps the most critical disadvantage of RF CMOS is the very high 1/f noise levels observed in MOSFETs in comparison to BJTs (bipolar-junction transistor). The silicon – silicondioxide interface is crucial to the operation of all MOSFETs, and unlike bipolar devices, MOSFETs are largely surface conductive devices, with device current flowing at or near the interface. This leads to the large 1/f noise associated with FETs. There has been on-going research to study the physical mechanism of 1/f noise. The compact models used to predict device noise in circuit simulations have also been improved. It has recently been observed that 1/f noise increases during the lifetime of a transistor. Also, large statistical variations in noise level have been reported. The existing models fail to explain such variability in 1/f noise. The work presented here extends the state-of-the art of 1/f noise modeling through experimental and theoretical analysis of noise reliability and statistics. A new model is developed based on a novel theory that investigates the relationship between the spatial profile of interface traps and the bias dependence of 1/f noise. The theory is tested against device noise measurements, as well as RF circuit phase noise measurements

RF CMOS quadrature voltage-controlled oscillator design using superharmonic coupling method.

Chung, Wai Fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 98-100).Abstracts in English and Chinese.摘要 --- p.IIIACKNOWLEDGEMENT --- p.IVCONTENTS --- p.VLIST OF FIGURES --- p.VIIILIST OF TABLES --- p.XLIST OF TABLES --- p.XChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Receiver Architecture --- p.3Chapter 1.2.1 --- Zero-IF Receivers --- p.4Chapter 1.2.2 --- Low-IF Receivers --- p.6Chapter 1.2.2.1 --- Hartley Architecture --- p.7Chapter 1.2.2.2 --- Weaver Architecture --- p.9Chapter 1.3 --- Image-rejection ratio --- p.10Chapter 1.4 --- Thesis Organization --- p.12Chapter CHAPTER 2 --- FUNDAMENTALS OF OSCILLATOR --- p.13Chapter 2.1 --- Basic Oscillator Theory --- p.13Chapter 2.2 --- Varactor --- p.15Chapter 2.3 --- Inductor --- p.17Chapter 2.4 --- Phase noise --- p.22Chapter 2.4.1 --- The Leeson ´ةs phase noise expression --- p.24Chapter 2.4.2 --- Linear model --- p.25Chapter 2.4.3 --- Linear Time-Variant phase noise model --- p.28Chapter CHAPTER 3 --- FULLY-INTEGRATED CMOS OSCILLATOR DESIGN --- p.31Chapter 3.1 --- Ring oscillator --- p.31Chapter 3.2 --- LC oscillator --- p.33Chapter 3.2.1 --- LC-tank resonator --- p.34Chapter 3.2.2 --- Negative transconductance --- p.36Chapter 3.3 --- Generation of quadrature phase signals --- p.39Chapter 3.4 --- Quadrature VCO topologies --- p.41Chapter 3.4.1 --- Parallel-coupled QVCO --- p.41Chapter 3.4.2 --- Series-coupled QVCO --- p.46Chapter 3.4.3 --- QVCO with Back-gate Coupling --- p.47Chapter 3.4.4 --- QVCO using superharmonic coupling --- p.49Chapter 3.5 --- Novel QVCO using back-gate superharmonic coupling --- p.52Chapter 3.5.1 --- Tuning range --- p.54Chapter 3.5.2 --- Negative gm --- p.55Chapter 3.5.3 --- Phase noise calculation --- p.56Chapter 3.5.4 --- Coupling coefficient --- p.57Chapter 3.5.5 --- Low-voltage and low-power design --- p.59Chapter 3.5.6 --- Layout Consideration --- p.61Chapter 3.5.6.1 --- Symmetrical Layout and parasitics --- p.61Chapter 3.5.6.2 --- Metal width and number of vias --- p.63Chapter 3.5.6.3 --- Substrate contact and guard ring --- p.63Chapter 3.5.7 --- Simulation Results --- p.65Chapter 3.5.7.1 --- Frequency and output power --- p.65Chapter 3.5.7.2 --- Quadrature signal generation --- p.67Chapter 3.5.7.3 --- Tuning range --- p.67Chapter 3.5.7.4 --- Power consumption --- p.68Chapter 3.5.7.5 --- Phase noise --- p.69Chapter 3.6 --- Polyphase filter and Single-sideband mixer design --- p.70Chapter 3.6.1 --- Polyphase filter --- p.72Chapter 3.6.2 --- Layout Consideration --- p.74Chapter 3.6.3 --- Simulation results --- p.76Chapter 3.7 --- Comparison with parallel-coupled QVCO --- p.78Chapter CHAPTER 4 --- EXPERIMENTAL RESULTS --- p.80Chapter 4.1 --- Test Fixture --- p.82Chapter 4.2 --- Measurement set-up --- p.84Chapter 4.3 --- Measurement results --- p.86Chapter 4.3.1 --- Proposed QVCO using back-gate superharmonic coupling --- p.86Chapter 4.3.1.1 --- Output Spectrum --- p.86Chapter 4.3.1.2 --- Tuning range --- p.87Chapter 4.3.1.3 --- Phase noise --- p.88Chapter 4.3.1.4 --- Power consumption --- p.88Chapter 4.3.1.5 --- Image-rejection ratio --- p.89Chapter 4.3.2 --- Parallel-coupled QVCO --- p.90Chapter 4.3.2.1 --- Output spectrum --- p.90Chapter 4.3.2.2 --- Power consumption --- p.90Chapter 4.3.2.3 --- Tuning range --- p.91Chapter 4.3.2.4 --- Phase noise --- p.92Chapter 4.3.3 --- Comparison between proposed and parallel-coupled QVCO --- p.93Chapter CHAPTER 5 --- CONCLUSIONS --- p.95Chapter 5.1 --- Conclusions --- p.95Chapter 5.2 --- Future work --- p.97REFERENCES --- p.9