829 research outputs found
A sub-mW IoT-endnode for always-on visual monitoring and smart triggering
This work presents a fully-programmable Internet of Things (IoT) visual
sensing node that targets sub-mW power consumption in always-on monitoring
scenarios. The system features a spatial-contrast binary
pixel imager with focal-plane processing. The sensor, when working at its
lowest power mode ( at 10 fps), provides as output the number of
changed pixels. Based on this information, a dedicated camera interface,
implemented on a low-power FPGA, wakes up an ultra-low-power parallel
processing unit to extract context-aware visual information. We evaluate the
smart sensor on three always-on visual triggering application scenarios.
Triggering accuracy comparable to RGB image sensors is achieved at nominal
lighting conditions, while consuming an average power between and
, depending on context activity. The digital sub-system is extremely
flexible, thanks to a fully-programmable digital signal processing engine, but
still achieves 19x lower power consumption compared to MCU-based cameras with
significantly lower on-board computing capabilities.Comment: 11 pages, 9 figures, submitteted to IEEE IoT Journa
An embedded adaptive optics real time controller
The design and realisation of a low cost, high speed control system for adaptive optics (AO) is presented. This control system is built around a field programmable gate array (FPGA). FPGA devices represent a fundamentally different approach to implementing control systems than conventional central processing units. The performance of the FPGA control system is demonstrated in a specifically constructed laboratory AO experiment where closed loop AO correction is shown. An alternative application of the control system is demonstrated in the field of optical tweezing, where it is used to study the motion dynamics of particles trapped within laser foci
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Near-sensor data analytics is a promising direction for IoT endpoints, as it
minimizes energy spent on communication and reduces network load - but it also
poses security concerns, as valuable data is stored or sent over the network at
various stages of the analytics pipeline. Using encryption to protect sensitive
data at the boundary of the on-chip analytics engine is a way to address data
security issues. To cope with the combined workload of analytics and encryption
in a tight power envelope, we propose Fulmine, a System-on-Chip based on a
tightly-coupled multi-core cluster augmented with specialized blocks for
compute-intensive data processing and encryption functions, supporting software
programmability for regular computing tasks. The Fulmine SoC, fabricated in
65nm technology, consumes less than 20mW on average at 0.8V achieving an
efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to
25MIPS/mW in software. As a strong argument for real-life flexible application
of our platform, we show experimental results for three secure analytics use
cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN
consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with
secured remote recognition in 5.74pJ/op; and seizure detection with encrypted
data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE
Transactions on Circuits and Systems - I: Regular Paper
A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization
A new generation of radio telescopes is achieving unprecedented levels of
sensitivity and resolution, as well as increased agility and field-of-view, by
employing high-performance digital signal processing hardware to phase and
correlate large numbers of antennas. The computational demands of these imaging
systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the
number of independent beams, and N is the number of antennas. The
specifications of many new arrays lead to demands in excess of tens of PetaOps
per second.
To meet this challenge, we have developed a general purpose correlator
architecture using standard 10-Gbit Ethernet switches to pass data between
flexible hardware modules containing Field Programmable Gate Array (FPGA)
chips. These chips are programmed using open-source signal processing libraries
we have developed to be flexible, scalable, and chip-independent. This work
reduces the time and cost of implementing a wide range of signal processing
systems, with correlators foremost among them,and facilitates upgrading to new
generations of processing technology. We present several correlator
deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes
parameter application deployed on the Precision Array for Probing the Epoch of
Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31
pages. v2: corrected typo, v3: corrected Fig. 1
A scalable packetised radio astronomy imager
Includes bibliographical referencesModern radio astronomy telescopes the world over require digital back-ends. The complexity of these systems depends on many site-specific factors, including the number of antennas, beams and frequency channels and the bandwidth to be processed. With the increasing popularity for ever larger interferometric arrays, the processing requirements for these back-ends have increased significantly. While the techniques for building these back-ends are well understood, every installation typically still takes many years to develop as the instruments use highly specialised, custom hardware in order to cope with the demanding engineering requirements. Modern technology has enabled reprogrammable FPGA-based processing boards, together with packet-based switching techniques, to perform all the digital signal processing requirements of a modern radio telescope array. The various instruments used by radio telescopes are functionally very different, but the component operations remain remarkably similar and many share core functionalities. Generic processing platforms are thus able to share signal processing libraries and can acquire different personalities to perform different functions simply by reprogramming them and rerouting the data appropriately. Furthermore, Ethernet-based packet-switched networks are highly flexible and scalable, enabling the same instrument design to be scaled to larger installations simply by adding additional processing nodes and larger network switches. The ability of a packetised network to transfer data to arbitrary processing nodes, along with these nodes' reconfigurability, allows for unrestrained partitioning of designs and resource allocation. This thesis describes the design and construction of the first working radio astronomy imaging instrument hosted on Ethernet-interconnected re- programmable FPGA hardware. I attempt to establish an optimal packetised architecture for the most popular instruments with particular attention to the core array functions of correlation and beamforming. Emphasis is placed on requirements for South Africa's MeerKAT array. A demonstration system is constructed and deployed on the KAT-7 array, MeerKAT's prototype. This research promises reduced instrument development time, lower costs, improved reliability and closer collaboration between telescope design teams
Signal Processing for an Autonomous Underwater Vehicle: an FPGA approach
The idea of this thesis comes out from the participation of the University of Central Florida to the Annual International Autonomous Underwater Vehicle Competition of 2007. The objective of this competition is to make the AUV to accomplish to a specific route. A part of this route expects the AUV to detect a ping and following it as a source. The objective of this thesis is to improve the performance of this trajectory tracking. A Field Programmable Logic Array will be used to perform an effective Digital Signal Processing
Reconfigurable hardware for the new generation IoT video-cards
Dissertação de mestrado em Engenharia Eletrónica Industrial e ComputadoresEmbedded systems became a crucial research and developing area because of the dependence of
society on devices and the growing demand for new technology products in our lives. The video industry
is an example of remarkable technological advances by exploiting the hardware performance for bringing
new video products along with even better video quality and higher resolution. Today is time for Ultra High
Definition (UHD) resolution and the next new feature is the 8k. A relevant area that may benefit from 8k is
medicine, by improving the detail and image quality in diagnoses. Moreover, Japan is preparing to become
the first 8k transmitter at the 2020 Olympics.
In spite of existing already general-purpose solutions for managing efficiently UHD video, the
deployment of a customized configurable solution can be useful for a specific system needs. Besides,
it may dictate market favorable positioning on meeting new market demands by providing faster upgrades.
For addressing this problem, this MSc thesis proposes a hardware-based deployment of two essential
reconfigurable cores for a new generation IoT UHD Video-Card, for managing huge memory accesses as
well as for compressing video. The memory management provides a memory direct access for dealing
with variable video resolution up to 8k, as well as data error control, frame alignment, configurable memory
region, and more. The video compression is performed by a configurable core based on an open-source
H.264 encoder. The results presented show it was achieved 8k real-time video streaming along with extra
control and status functionalities. Video encoding was achieved for up to 8k.Os sistemas embebidos tornaram-se uma área fulcral de pesquisa e desenvolvimento devido à
dependência da sociedade em dispositivos e à crescente procura por novidades tecnológicas para o
quotidiano. A indústria de vídeo é um exemplo do notável avanço tecnológico ao explorar o desempenho
máximo do hardware para trazer maior qualidade de vídeo e maior resolução. A resolução de vídeo UHD já
é uma realidade e a próxima novidade é o 8k. Uma área de relevo que pode beneficiar do 8k é a medicina,
com maior detalhe e qualidade de imagem em diagnósticos. Além disso, o Japão está preparar-se para
se tornar o primeiro transmissor de 8k nas Olimpíadas de 2020.
Apesar de existirem soluções capazes de gerir com eficiência vídeo UHD, uma solução personalizada
e configurável pode ser útil para as necessidades específicas de um sistema. Além disso, pode ditar um
posicionamento dianteiro no mercado ao atender às novas exigências do mercado fornecendo novidades
mais rapidamente.
Como possível solução para os problemas expostos, esta tese propõe o desenvolvimento de dois
núcleos de hardware reconfigurável essenciais para uma nova geração de placas IoT de vídeo UHD, para
gerir acessos à memória assim como para compactar vídeo. A gestão de memória desenvolvida fornece
acesso direto à memória para lidar com resolução de vídeo variável e até 8k, além de controlo de erros de
dados, alinhamento de frames, região de memória configurável e muito mais. A compactação de vídeo
é realizada por um núcleo de hardware configurável, baseado num Encoder H.264 de código aberto. Os
resultados mostram que foi alcançada transmissão de vídeo 8k em tempo real, além de funcionalidades
extras de controlo e estado. A codificação de vídeo até 8k foi alcançada
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