Receptores de rádio-frequência melhorados e disruptivos

This Ph.D. mainly addresses the reception part of a radio front end, focusing on Radio Frequency (RF) sampling architectures. These are considered to be the most promising future candidates to get better performance in terms of bandwidth and agility, following the well-known Software-Defined Radio (SDR) concept. The study considers the usage of an RF receiver in a standalone operation, i.e., used for receiving unknown data at the antenna, and when used as observation path for Power Amplifier (PA) linearization via Digital Predistortion (DPD), since nowadays this represents a mandatory technique to increase overall system’s performance. Firstly, commercial available RF Analog-Digital-Converters (ADCs) are studied and characterized to understand their limitations when used in DPD scenarios. A method for characterization and digital post-compensation to improve performance is proposed and evaluated. Secondly, an innovative FPGA-based RF single-bit pulsed converter based on Pulse Width Modulation (PWM) is addressed targeting frequency agility, high analog input bandwidth, and system integration, taking profit of an FPGA-based implementation. The latter was optimized based on PWM theoretical behavior maximizing Signal-to-Noise-Ratio (SNR) and bandwidth. The optimized receiver, was afterwards evaluated in a 5G C-RAN architecture and as a feedback loop for DPD. Finally, a brief study regarding DPD feedback loops in the scope of multiantenna transmitters is presented. This Ph.D. contributes with several advances to the state-of-the-art of SDR receiver, and to the so-called SDR DPD concept.Este doutoramento endereça principalmente a componente de receção de um transcetor de rádio-frequência (RF), focando-se em arquiteturas de receção de amostragem em RF. Estas são assim consideradas como sendo as mais promissoras para o futuro, em termos de desempenho, largura de banda e agilidade, de acordo com o conhecido conceito de Rádios Definidos por Software (SDR). O estudo considera o uso dos recetores de RF em modo standalone, i.e., recebendo dados desconhecidos provenientes da antena, e também quando usados como caminho de observação para aplicação de linearização de amplificadores de potência (PAs) via pré-distorção digital (DPD), pois atualmente esta é uma técnica fundamental para aumentar o desempenho geral do sistema. Em primeiro lugar, os conversores analógico-digital de RF são estudados e caracterizados para perceber as suas limitações quando usados em cenários de DPD. Um método de caracterização e pós compensação digital é proposto para obter melhorias de desempenho. Em segundo lugar, um novo recetor pulsado de um bit baseado em Modulação de Largura de Pulso (PWM) e implementado em Agregado de Células Lógicas Programáveis (FPGA) é endereçado, visando agilidade em frequência, largura de banda analógica e integração de sistema, tirando proveito da implementação em FPGA. Este recetor foi otimizado com base no modelo comportamental teórico da modulação PWM, maximizando a relação sinalruído (SNR) e a largura de banda. O recetor otimizado foi posteriormente avaliado num cenário 5G de uma arquitetura C-RAN e também num cenário em que serve de caminho de observação para DPD. Finalmente, um breve estudo relativo a caminhos de observação de DPD no contexto de transmissores multi-antena é também apresentado. Este doutoramento contribui com vários avanços no estado da arte de recetores SDR e no conceito de SDR DPD.Programa Doutoral em Engenharia Eletrotécnic

Subsampling receivers with applications to software defined radio systems

Este trabajo de tesis propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estándar y SDR (Software Defined Radio). El objetivo principal será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, así como la reducción de los costes totales de los receptores de comunicación y de los equipos de certificación que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como la idea de la tecnología SDR es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidores analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarían sin perder resolución para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de sistemas debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando estas arquitecturas, este componente procesará la señal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las técnicas de submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificación de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analógico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso diseñada y fabricada, y cuya caracterización experimental muestra una resolución de más 8 bits para un ancho de banda analógico de 20 MHz. Concretamente, la resolución medida será mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estándares de comunicaciones inalámbricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido térmico) y una dificultad añadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interés, esta tesis propone el uso de una técnica basada en una arquitectura de reloj múltiple con el objetivo de aumentar la resolución y cubrir un número mayor de estándares para su test y certificación. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguirá reducir este efecto, aumentando la resolución en aproximadamente 0.5-1 bit respecto al caso de sólo usar una fuente de reloj. Las expresiones teóricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis también propone novedosas técnicas para la aplicación de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafíos adicionales por el hecho de existir la posibilidad de solapamiento entre la señal de interés y los otros canales de comunicación, así como de solapamiento con sus armónicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo técnicas para la elección de la frecuencia óptima de muestreo que evitan el solapamiento entre señales, a la vez que consiguen incrementar la resolución del receptor. Finalmente, se presentará la optimización en cuanto a características de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estará basado en las técnicas de reloj múltiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema diseñado podrá emplearse para diversas aplicaciones a ambos lados de la cadena de comunicación, tal como en receptores de detección de espectro para radio cognitiva, o implementando el bucle de realimentación de un transmisor para la linealización de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseño de un prototipo de recepción multi-estándar basado en submuestreo para aplicaciones de test y certificación. La segunda aportación es la dedicada a la optimización de las especificaciones de ruido a partir de las técnicas presentadas basadas en reloj múltiple. Por último, la tercera contribución principal es la relacionada con la extensión de este tipo de técnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teóricamente y experimentalmente validadas

Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters

This thesis is focusing on developing a compact digital predistortion (DPD) system which costs less DPD added power consumptions. It explores a new theory and techniques to relieve the requirement of the number of training samples and the sampling-rate of feedback ADCs in DPD systems. A new theory about the information carried by training samples is introduced. It connects the generalized error of the DPD estimation algorithm with the statistical properties of modulated signals. Secondly, based on the proposed theory, this work introduces a compressed sample selection method to reduce the number of training samples by only selecting the minimal samples which satisfy the foreknown probability information. The number of training samples and complex multiplication operations required for coefficients estimation can be reduced by more than ten times without additional calculation resource. Thirdly, based on the proposed theory, this thesis proves that theoretically a DPD system using memory polynomial based behavioural modes and least-square (LS) based algorithms can be performed with any sampling-rate of feedback samples. The principle, implementation and practical concerns of the undersampling DPD which uses lower sampling-rate ADC are then introduced. Finally, the observation bandwidth of DPD systems can be extended by the proposed multi-rate track-and-hold circuits with the associated algorithm. By addressing several parameters of ADC and corresponding DPD algorithm, multi-GHz observation bandwidth using only a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization performance of multi-band and continued wideband RF transmitter applications via extensive experimental tests

Frequency diversity wideband digital receiver and signal processor for solid-state dual-polarimetric weather radars

2012 Summer.Includes bibliographical references.The recent spate in the use of solid-state transmitters for weather radar systems has unexceptionably revolutionized the research in meteorology. The solid-state transmitters allow transmission of low peak powers without losing the radar range resolution by allowing the use of pulse compression waveforms. In this research, a novel frequency-diversity wideband waveform is proposed and realized to extenuate the low sensitivity of solid-state radars and mitigate the blind range problem tied with the longer pulse compression waveforms. The latest developments in the computing landscape have permitted the design of wideband digital receivers which can process this novel waveform on Field Programmable Gate Array (FPGA) chips. In terms of signal processing, wideband systems are generally characterized by the fact that the bandwidth of the signal of interest is comparable to the sampled bandwidth; that is, a band of frequencies must be selected and filtered out from a comparable spectral window in which the signal might occur. The development of such a wideband digital receiver opens a window for exciting research opportunities for improved estimation of precipitation measurements for higher frequency systems such as X, Ku and Ka bands, satellite-borne radars and other solid-state ground-based radars. This research describes various unique challenges associated with the design of a multi-channel wideband receiver. The receiver consists of twelve channels which simultaneously downconvert and filter the digitized intermediate-frequency (IF) signal for radar data processing. The product processing for the multi-channel digital receiver mandates a software and network architecture which provides for generating and archiving a single meteorological product profile culled from multi-pulse profiles at an increased data date. The multi-channel digital receiver also continuously samples the transmit pulse for calibration of radar receiver gain and transmit power. The multi-channel digital receiver has been successfully deployed as a key component in the recently developed National Aeronautical and Space Administration (NASA) Global Precipitation Measurement (GPM) Dual-Frequency Dual-Polarization Doppler Radar (D3R). The D3R is the principal ground validation instrument for the precipitation measurements of the Dual Precipitation Radar (DPR) onboard the GPM Core Observatory satellite scheduled for launch in 2014. The D3R system employs two broadly separated frequencies at Ku- and Ka-bands that together make measurements for precipitation types which need higher sensitivity such as light rain, drizzle and snow. This research describes unique design space to configure the digital receiver for D3R at several processing levels. At length, this research presents analysis and results obtained by employing the multi-carrier waveforms for D3R during the 2012 GPM Cold-Season Precipitation Experiment (GCPEx) campaign in Canada

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Design and analysis of multi-element antenna systems and agile radiofrequency frontends for automotive applications

Vehicular connectivity serves as one of the major enabling technologies for current applications like driver assistance, safety and infotainment as well as upcoming features like highly automated vehicles - all of which having certain quality of service requirements, e. g. datarate or reliability. This work focuses on vehicular integration of multiple-input-multiple-output (MIMO) capable multielement antenna systems and frequency-agile radio frequency (RF) front ends to cover current and upcoming connectivity needs. It is divided in four major parts. For each part, mostly physical layer effects are analyzed (any performance lost on physical layer, cannot be compensated in higher layers), sensitivities are identified and novel concepts are introduced based on the status-quo findings.Fahrzeugvernetzung dient als eine der wesentlichsten Befähigungstechnologien für moderne Fahrerassistenzsysteme und zukünftig auch hochautomatisiertes Fahren. Sowohl die heutigen als auch zukünftige Anwendungen haben besondere Dienstgüteanforderungen, z.B. in Bezug auf die Datenrate oder Verlässlichkeit. Im Rahmen dieser Arbeit wird die Integration von Mehrantennensystemen für MIMO-Funkanwendungen (MIMO: engl. Multiple Input Multiple Output) sowie von frequenzagilen Hochfrequenzfrontends im Fahrzeugumfeld untersucht, um so eine technische Grundlage für zukünftige Anforderungen an die automobile Vernetzung anbieten zu können. Die dabei gewonnenen Erkenntnisse lassen sich in vier Teile gliedern. Grundsätzlich konzentrieren sich die Untersuchungen vorrangig auf die physikalische Ebene. Auf Basis des aktuellen Status Quo werden Sensitivitäten herausgearbeitet, neue Konzepte hergeleitet und entwickelt