124 research outputs found
Resource-aware scheduling for 2D/3D multi-/many-core processor-memory systems
This dissertation addresses the complexities of 2D/3D multi-/many-core processor-memory systems, focusing on two key areas: enhancing timing predictability in real-time multi-core processors and optimizing performance within thermal constraints. The integration of an increasing number of transistors into compact chip designs, while boosting computational capacity, presents challenges in resource contention and thermal management. The first part of the thesis improves timing predictability. We enhance shared cache interference analysis for set-associative caches, advancing the calculation of Worst-Case Execution Time (WCET). This development enables accurate assessment of cache interference and the effectiveness of partitioned schedulers in real-world scenarios. We introduce TCPS, a novel task and cache-aware partitioned scheduler that optimizes cache partitioning based on task-specific WCET sensitivity, leading to improved schedulability and predictability. Our research explores various cache and scheduling configurations, providing insights into their performance trade-offs. The second part focuses on thermal management in 2D/3D many-core systems. Recognizing the limitations of Dynamic Voltage and Frequency Scaling (DVFS) in S-NUCA many-core processors, we propose synchronous thread migrations as a thermal management strategy. This approach culminates in the HotPotato scheduler, which balances performance and thermal safety. We also introduce 3D-TTP, a transient temperature-aware power budgeting strategy for 3D-stacked systems, reducing the need for Dynamic Thermal Management (DTM) activation. Finally, we present 3QUTM, a novel method for 3D-stacked systems that combines core DVFS and memory bank Low Power Modes with a learning algorithm, optimizing response times within thermal limits. This research contributes significantly to enhancing performance and thermal management in advanced processor-memory systems
Using Simultaneous Multithreading to Support Real-Time Scheduling
The goal of real-time scheduling is to find a way to schedule every program in a specified system without unacceptable deadline misses. If doing so on a given hardware platform is not possible, then the question to ask is ``What can be changed?'' Simultaneous multithreading (SMT) is a technology that allows a single computer core to execute multiple programs at once, at the cost of increasing the time required to execute individual programs. SMT has been shown to improve performance in many areas of computing, but SMT has seen little application to the real-time domain. Reasons for not using SMT in real-time systems include the difficulty of knowing how much execution time a program will require when SMT is in use, concerns that longer execution times could cause unacceptable deadline misses, and the difficulty of deciding which programs should and should not use SMT to share a core. This dissertation shows how SMT can be used to support real-time scheduling in both the hard real-time (HRT) case, where deadline misses are never acceptable, and the soft real-time (SRT) case, where deadline misses are undesirable but tolerable. Contributions can be divided into three categories. First, the effects of SMT on execution times are measured and parameters for modeling the effects of SMT are given. Second, scheduling algorithms for the SRT case that take advantage of SMT are given and evaluated. Third, scheduling algorithms for the HRT case are given and evaluated. In both the SRT and HRT cases, using the proposed algorithms do not lead to unacceptable deadline misses and can have effects similar to increasing a platform's core count by a third or more.Doctor of Philosoph
Fundamentals
Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters
Analysis of Embedded Controllers Subject to Computational Overruns
Microcontrollers have become an integral part of modern everyday embedded systems, such as smart bikes, cars, and drones. Typically, microcontrollers operate under real-time constraints, which require the timely execution of programs on the resource-constrained hardware. As embedded systems are becoming increasingly more complex, microcontrollers run the risk of violating their timing constraints, i.e., overrunning the program deadlines. Breaking these constraints can cause severe damage to both the embedded system and the humans interacting with the device. Therefore, it is crucial to analyse embedded systems properly to ensure that they do not pose any significant danger if the microcontroller overruns a few deadlines.However, there are very few tools available for assessing the safety and performance of embedded control systems when considering the implementation of the microcontroller. This thesis aims to fill this gap in the literature by presenting five papers on the analysis of embedded controllers subject to computational overruns. Details about the real-time operating system's implementation are included into the analysis, such as what happens to the controller's internal state representation when the timing constraints are violated. The contribution includes theoretical and computational tools for analysing the embedded system's stability, performance, and real-time properties.The embedded controller is analysed under three different types of timing violations: blackout events (when no control computation is completed during long periods), weakly-hard constraints (when the number of deadline overruns is constrained over a window), and stochastic overruns (when violations of timing constraints are governed by a probabilistic process). These scenarios are combined with different implementation policies to reduce the gap between the analysis and its practical applicability. The analyses are further validated with a comprehensive experimental campaign performed on both a set of physical processes and multiple simulations.In conclusion, the findings of this thesis reveal that the effect deadline overruns have on the embedded system heavily depends the implementation details and the system's dynamics. Additionally, the stability analysis of embedded controllers subject to deadline overruns is typically conservative, implying that additional insights can be gained by also analysing the system's performance
Mixed Criticality Systems - A Review : (13th Edition, February 2022)
This review covers research on the topic of mixed criticality systems that has been published since Vestal’s 2007 paper. It covers the period up to end of 2021. The review is organised into the following topics: introduction and motivation, models, single processor analysis (including job-based, hard and soft tasks, fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, related topics, realistic models, formal treatments, systems issues, industrial practice and research beyond mixed-criticality. A list of PhDs awarded for research relating to mixed-criticality systems is also included
WCET and Priority Assignment Analysis of Real-Time Systems using Search and Machine Learning
Real-time systems have become indispensable for human life as they are used in numerous industries, such as vehicles, medical devices, and satellite systems. These systems are very sensitive to violations of their time constraints (deadlines), which can have catastrophic consequences. To verify whether the systems meet their time constraints, engineers perform schedulability analysis from early stages and throughout development. However, there are challenges in obtaining precise results from schedulability analysis due to estimating the worst-case execution times (WCETs) and assigning optimal priorities to tasks.
Estimating WCET is an important activity at early design stages of real-time systems. Based on such WCET estimates, engineers make design and implementation decisions to ensure that task executions always complete before their specified deadlines. However, in practice, engineers often cannot provide a precise point of WCET estimates and they prefer to provide plausible WCET ranges.
Task priority assignment is an important decision, as it determines the order of task executions and it has a substantial impact on schedulability results. It thus requires finding optimal priority assignments so that tasks not only complete their execution but also maximize the safety margins from their deadlines. Optimal priority values increase the tolerance of real-time systems to unexpected overheads in task executions so that they can still meet their deadlines. However, it is a hard problem to find optimal priority assignments because their evaluation relies on uncertain WCET values and complex engineering constraints must be accounted for.
This dissertation proposes three approaches to estimate WCET and assign optimal priorities at design stages. Combining a genetic algorithm and logistic regression, we first suggest an automatic approach to infer safe WCET ranges with a probabilistic guarantee based on the worst-case scheduling scenarios. We then introduce an extended approach to account for weakly hard real-time systems with an industrial schedule simulator. We evaluate our approaches by applying them to industrial systems from different domains and several synthetic systems. The results suggest that they are possible to estimate probabilistic safe WCET ranges efficiently and accurately so the deadline constraints are likely to be satisfied with a high degree of confidence. Moreover, we propose an automated technique that aims to identify the best possible priority assignments in real-time systems. The approach deals with multiple objectives regarding safety margins and engineering constraints using a coevolutionary algorithm. Evaluation with synthetic and industrial systems shows that the approach significantly outperforms both a baseline approach and solutions defined by practitioners. All the solutions in this dissertation scale to complex industrial systems for offline analysis within an acceptable time, i.e., at most 27 hours
MACHINE LEARNING IN THE DESIGN SPACE EXPLORATION OF TSN NETWORKS
Real-time systems are systems that have specific timing requirements. They are critical systems that play an important role in modern societies, be it for instance control systems in factories or automotives. In recent years, Ethernet has been increasingly adopted as layer 2 protocol in real-time systems. Indeed, the adoption of Ethernet provides many benefits, including COTS and cost-effective components, high data rates and flexible topology. The main drawback of Ethernet is that it does not offer "out-of-the-box" mechanisms to guarantee timing and reliability constraints. This is the reason why time-sensitive networking (TSN) mechanisms have been introduced to provide Quality-of-Service (QoS) on top of Ethernet and satisfy the requirements of real-time communication in critical systems. The promise of Ethernet TSN is the possibility to use a single network for different criticality levels, e.g, critical control traffic and infotainment traffic sharing the same network resources.
This thesis is about the design of Ethernet TSN networks, and specifically about techniques that help quantify the extent to which a network can support current and future communication needs. The context of this work is the increasing use of design-space exploration (DSE) in the industry to master the complexity of designing (e.g. in terms of architectural and technological choices) and configuring a TSN network. One of the main steps in DSE is performing schedulability analysis to conclude about the feasibility of a network configuration, i.e., whether all traffic streams satisfy their timing constraints. This step can take weeks of computations for a large set of candidate solutions with the simplest TSN mechanisms, while more complicated TSN mechanisms will require even longer time.
This thesis explores the use of Artificial Intelligence (AI) techniques to assist in the design of TSN networks by speeding up the DSE. Specifically, the thesis proposes the use of machine learning (ML) as an alternative approach to schedulability analysis. The application of ML involves two steps. In the first step, ML algorithms are trained with a large set of TSN configurations labeled as feasible or non-feasible. Due to its pattern recognition ability, ML algorithms can predict the feasibility of unseen configurations with a good accuracy. Importantly, the execution time of an ML model is only a fraction of conventional schedulability analysis and remains constant whatever the complexity of the network configurations.
Several contributions make up the body of the thesis. In the first contribution, we observe that the topology and the traffic of a TSN network can be used to derive simple features that are relevant to the network feasibility. Therefore, standard and simple machine learning (ML) algorithms such as k-Nearest Neighbors are used to take these features as inputs and predict the feasibility of TSN networks. This study suggests that ML algorithms can provide a viable alternative to conventional schedulability analysis due to fast execution time and high prediction accuracy. A hybrid approach combining ML and schedulability analyses is also introduced to control the prediction uncertainty.
In the next studies, we aim at further automating the feasibility prediction of TSN networks with the Graph Neural Network (GNN) model. GNN takes as inputs the raw data from the TSN configurations and encodes them as graphs. Synthetic features are generated by GNN, thus the manual feature selection step is eliminated. More importantly, the GNN model can generalize to a wide range of topologies and traffic patterns, in contrast to the standard ML algorithms tested before that can only work with a fixed topology. An ensemble of individual GNN models shows high prediction accuracies on many test cases containing realistic automotive topologies. We also explore possibilities to improve the performance of GNN with more advanced deep learning techniques. In particular, semi-supervised learning and self-supervised learning are experimented. Although these learning paradigms provide modest improvements, we consider them promising techniques due to the ability to leverage the massive amount of unlabeled training data.
While this thesis focuses on the feasibility prediction of TSN configurations, AI techniques have huge potentials to automate other tasks in real-time systems. A natural follow-up work of this thesis is to apply GNN to multiple TSN mechanisms and predict which mechanism can provide the best scheduling solution for a given configuration. Although we need distinct ML models for each TSN mechanism, this research direction is promising as TSN mechanisms may share similar feasibility features and thus transfer learning techniques can be applied to facilitate the training process. Furthermore, GNN can be used as a core block in deep reinforcement learning to find the feasible priority assignment of TSN configurations. This thesis aims to make a contribution towards DSE of TSN networks with AI
A survey of techniques for reducing interference in real-time applications on multicore platforms
This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.This work was supported in part by the Comunidad de Madrid Government "Nuevas Técnicas de Desarrollo de Software de Tiempo Real Embarcado Para Plataformas. MPSoC de Próxima Generación" under Grant IND2019/TIC-17261
LIPIcs, Volume 248, ISAAC 2022, Complete Volume
LIPIcs, Volume 248, ISAAC 2022, Complete Volum
Optimal Priority Assignment for Real-Time Systems: A Coevolution-Based Approach
In real-time systems, priorities assigned to real-time tasks determine the order of task executions, by relying on an underlying task scheduling policy. Assigning optimal priority values to tasks is critical to allow the tasks to complete their executions while maximizing safety margins from their specified deadlines. This enables real-time systems to tolerate unexpected overheads in task executions and still meet their deadlines. In practice, priority assignments result from an interactive process between the development and testing teams. In this article, we propose an automated method that aims to identify the best possible priority assignments in real-time systems, accounting for multiple objectives regarding safety margins and engineering constraints. Our approach is based on a multi-objective, competitive coevolutionary algorithm mimicking the interactive priority assignment process between the development and testing teams. We evaluate our approach by applying it to six industrial systems from different domains and several synthetic systems. The results indicate that our approach significantly outperforms both our baselines, i.e., random search and sequential search, and solutions defined by practitioners. Our approach scales to complex industrial systems as an offline analysis method that attempts to find near-optimal solutions within acceptable time, i.e., less than 16 hours
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