Chemical vapor deposited two-dimensional material based high frequency flexible field-effect transistors

Flexible nanoelectronics have attracted great attention due to interesting concepts such as wearable electronics and internet of things, which requires high speed and low power consumption flexible smart system with functions ranging from sensing, computing to wireless communicating. In this dissertation, transparent and solution processable nanoscale polyimide film for highly flexible gate dielectrics is demonstrated by in-situ opto-electro-mechanical measurement and utilized for two-dimensional nanomaterials based field-effect transistors (FETs). Graphene thin film transistor with the nanoscale polyimide dielectric on flexible glass is operated in extremely high frequency regime and shows the highest experimental saturation velocity (~8.4 × 10⁶ cm/s) in any materials in any flexible transistors. Molybdenum disulfide (MoS₂) based transistors with embedded gate structure on rigid substrate are demonstrated with enhancement mode operation, ON/OFF ratio over 10⁸, the highest transconductance (~ 70 µS/µm) and saturation velocity (~1.8 × 10⁶ cm/s). CVD MoS₂ FETs on flexible plastic substrates are also demonstrated, showing enhancement mode operation, ON/OFF radio over 10¹⁰ and transconductance (~6 µS/µm). The flexible CVD MoS₂ transistors with embedded gate structure were employed to study effects of substoichiometric doping by HfO [subscript 2-x]. After the doping layer, the flexible MoS₂ transistors show ×8 higher source-drain current density as well as more than ×2 mobility improvements. For the another first demonstration, GHz operation and flexibility of graphene and MoS₂ based FETs are realized on commercial available paper substrates, which indicates flexible two-dimensional material based nanoelectronics can be implemented on paper substrates for systems, sensors, and Internet of Things.Electrical and Computer Engineerin

An investigation of nanoscale materials and their incorporation in patch antenna for high frequency applications

The rapid development in the polymer-based electronic contribute a strong determination for using these materials as substitute to the high-cost materials commonly used as medium substrate in the fabrication of Microstrip Patch Antenna (MPA). Antenna technology can strongly gain from the utilisation of low-cost, flexible, light weight with suitable fabrication techniques. The uniqueness of this work is the use of variety of common but unexplored different polymer materials such as Polyethylene (PE), Polypropylene (PP), Polyvinyl chloride, (PVC) Polystyrene (PS), Polystyrene fibre (PSF) as the substrates for the design and fabrication of different MPAs for communication and sensing applications in millimetre wave (MMW)region. Electrospinning (ES) technique is used to reconstruct PS and produced PSF material of low dielectric constant. A co-solvent vehicle(comprising 50:50 ratio) of Dichloromethane (DCM) and acetone was utilised with processing condition of solution infusion flow-rate of 60μL/min and an applied voltage of 12± kV yielded rigid PSF substrates. The PSF Produced has complex permittivity of 1.36±5% and a loss tangent of 2.4E-04±4.8E-04 which was measured using Spilt-Post Dielectric Resonators (SPDR) technique at National Physics Laboratory, Teddington, London. A diamond-shaped MPAs on RT Duriod material were simulated and fabricated using photo-lithography for different inner lengths to work in the frequencies range from (1-10 GHz). The resonant frequency is approximated as a function of inner length L1 in the form of a polynomial equation. The fabricated diamond-shaped MPA more compact (physical geometry) as compared with a traditional monopole antenna. This MPAs experimentally measured and have a good agreement with the simulated results. The coplanar waveguide (CPW) diamond-shaped MPA working in the MMW region was designed and fabricated with polymer materials as substrates using thermal evaporation technique and the RF measurement was carried out using Vector Network Analyser (VNA). The resonant frequencies of the CPW diamond shaped MPAs for (PE, PP, PVC, PS and PSF) were found to be 67.5 GHz, 72.36 GHz, 62.41 GHz, 63.25 GHz and 80.58 GHz, respectively. The antenna fabricated on PSF were resonating at higher frequency when compared to the other polymers materials. In adding an air-bridge to the CPW diamond-shaped MPA the resonating frequency increased from ≈55 GHz to≈ 62 GHz. Three different shaped nano-patch antennas (Diamond shaped, diamond shaped array and T-shaped) have been designed, simulated and fabricated on Silicon substrate with DLC deposition using focused Ion Beam (FIB) technique, these antennas were found to resonate at 1.42 THz with (-19 dB return loss), 2.42 THz with (-14 dB return loss) and 1.3 THz with (-45 dB return loss) respectively

Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version

Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Photodetectors

In this book some recent advances in development of photodetectors and photodetection systems for specific applications are included. In the first section of the book nine different types of photodetectors and their characteristics are presented. Next, some theoretical aspects and simulations are discussed. The last eight chapters are devoted to the development of photodetection systems for imaging, particle size analysis, transfers of time, measurement of vibrations, magnetic field, polarization of light, and particle energy. The book is addressed to students, engineers, and researchers working in the field of photonics and advanced technologies

Accurate quantum transport modelling and epitaxial structure design of high-speed and high-power In0.53Ga0.47As/AlAs double-barrier resonant tunnelling diodes for 300-GHz oscillator sources

Terahertz (THz) wave technology is envisioned as an appealing and conceivable solution in the context of several potential high-impact applications, including sixth generation (6G) and beyond consumer-oriented ultra-broadband multi-gigabit wireless data-links, as well as highresolution imaging, radar, and spectroscopy apparatuses employable in biomedicine, industrial processes, security/defence, and material science. Despite the technological challenges posed by the THz gap, recent scientific advancements suggest the practical viability of THz systems. However, the development of transmitters (Tx) and receivers (Rx) based on compact semiconductor devices operating at THz frequencies is urgently demanded to meet the performance requirements calling from emerging THz applications. Although several are the promising candidates, including high-speed III-V transistors and photo-diodes, resonant tunnelling diode (RTD) technology offers a compact and high performance option in many practical scenarios. However, the main weakness of the technology is currently represented by the low output power capability of RTD THz Tx, which is mainly caused by the underdeveloped and non-optimal device, as well as circuit, design implementation approaches. Indeed, indium phosphide (InP) RTD devices can nowadays deliver only up to around 1 mW of radio-frequency (RF) power at around 300 GHz. In the context of THz wireless data-links, this severely impacts the Tx performance, limiting communication distance and data transfer capabilities which, at the current time, are of the order of few tens of gigabit per second below around 1 m. However, recent research studies suggest that several milliwatt of output power are required to achieve bit-rate capabilities of several tens of gigabits per second and beyond, and to reach several metres of communication distance in common operating conditions. Currently, the shortterm target is set to 5−10 mW of output power at around 300 GHz carrier waves, which would allow bit-rates in excess of 100 Gb/s, as well as wireless communications well above 5 m distance, in first-stage short-range scenarios. In order to reach it, maximisation of the RTD highfrequency RF power capability is of utmost importance. Despite that, reliable epitaxial structure design approaches, as well as accurate physical-based numerical simulation tools, aimed at RF power maximisation in the 300 GHz-band are lacking at the current time. This work aims at proposing practical solutions to address the aforementioned issues. First, a physical-based simulation methodology was developed to accurately and reliably simulate the static current-voltage (IV ) characteristic of indium gallium arsenide/aluminium arsenide (In-GaAs/AlAs) double-barrier RTD devices. The approach relies on the non-equilibrium Green’s function (NEGF) formalism implemented in Silvaco Atlas technology computer-aided design (TCAD) simulation package, requires low computational budget, and allows to correctly model In0.53Ga0.47As/AlAs RTD devices, which are pseudomorphically-grown on lattice-matched to InP substrates, and are commonly employed in oscillators working at around 300 GHz. By selecting the appropriate physical models, and by retrieving the correct materials parameters, together with a suitable discretisation of the associated heterostructure spatial domain through finite-elements, it is shown, by comparing simulation data with experimental results, that the developed numerical approach can reliably compute several quantities of interest that characterise the DC IV curve negative differential resistance (NDR) region, including peak current, peak voltage, and voltage swing, all of which are key parameters in RTD oscillator design. The demonstrated simulation approach was then used to study the impact of epitaxial structure design parameters, including those characterising the double-barrier quantum well, as well as emitter and collector regions, on the electrical properties of the RTD device. In particular, a comprehensive simulation analysis was conducted, and the retrieved output trends discussed based on the heterostructure band diagram, transmission coefficient energy spectrum, charge distribution, and DC current-density voltage (JV) curve. General design guidelines aimed at enhancing the RTD device maximum RF power gain capability are then deduced and discussed. To validate the proposed epitaxial design approach, an In0.53Ga0.47As/AlAs double-barrier RTD epitaxial structure providing several milliwatt of RF power was designed by employing the developed simulation methodology, and experimentally-investigated through the microfabrication of RTD devices and subsequent high-frequency characterisation up to 110 GHz. The analysis, which included fabrication optimisation, reveals an expected RF power performance of up to around 5 mW and 10 mW at 300 GHz for 25 μm2 and 49 μm2-large RTD devices, respectively, which is up to five times higher compared to the current state-of-the-art. Finally, in order to prove the practical employability of the proposed RTDs in oscillator circuits realised employing low-cost photo-lithography, both coplanar waveguide and microstrip inductive stubs are designed through a full three-dimensional electromagnetic simulation analysis. In summary, this work makes and important contribution to the rapidly evolving field of THz RTD technology, and demonstrates the practical feasibility of 300-GHz high-power RTD devices realisation, which will underpin the future development of Tx systems capable of the power levels required in the forthcoming THz applications