Non-invasive Techniques Towards Recovering Highly Secure Unclonable Cryptographic Keys and Detecting Counterfeit Memory Chips

Due to the ubiquitous presence of memory components in all electronic computing systems, memory-based signatures are considered low-cost alternatives to generate unique device identifiers (IDs) and cryptographic keys. On the one hand, this unique device ID can potentially be used to identify major types of device counterfeitings such as remarked, overproduced, and cloned. On the other hand, memory-based cryptographic keys are commercially used in many cryptographic applications such as securing software IP, encrypting key vault, anchoring device root of trust, and device authentication for could services. As memory components generate this signature in runtime rather than storing them in memory, an attacker cannot clone/copy the signature and reuse them in malicious activity. However, to ensure the desired level of security, signatures generated from two different memory chips should be completely random and uncorrelated from each other. Traditionally, memory-based signatures are considered unique and uncorrelated due to the random variation in the manufacturing process. Unfortunately, in previous studies, many deterministic components of the manufacturing process, such as memory architecture, layout, systematic process variation, device package, are ignored. This dissertation shows that these deterministic factors can significantly correlate two memory signatures if those two memory chips share the same manufacturing resources (i.e., manufacturing facility, specification set, design file, etc.). We demonstrate that this signature correlation can be used to detect major counterfeit types in a non-invasive and low-cost manner. Furthermore, we use this signature correlation as side-channel information to attack memory-based cryptographic keys. We validate our contribution by collecting data from several commercially available off-the-shelf (COTS) memory chips/modules and considering different usage-case scenarios

What's wrong with Psychology, anyway?

This chapter considers various factors that have been responsible for the comparatively slow development of psychology into a cumulative empirical science. Special attention is devoted to correctable methodological mistakes, the over-reliance upon significance testing (and the fact that, in psychology, the null hypothesis is almost always false), and an analysis of the concept of replication

A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler

Hierarchical temporal memory (HTM) is a biomimetic machine learning algorithm focused upon modeling the structural and algorithmic properties of the neocortex. It is comprised of two components, realizing pattern recognition of spatial and temporal data, respectively. HTM research has gained momentum in recent years, leading to both hardware and software exploration of its algorithmic formulation. Previous work on HTM has centered on addressing performance concerns; however, the memory-bound operation of HTM presents significant challenges to scalability. In this work, a scalable flash-based storage processor unit, Flash-HTM (FHTM), is presented along with a detailed analysis of its potential scalability. FHTM leverages SSD flash technology to implement the HTM cortical learning algorithm spatial pooler. The ability for FHTM to scale with increasing model complexity is addressed with respect to design footprint, memory organization, and power efficiency. Additionally, a mathematical model of the hardware is evaluated against the MNIST dataset, yielding 91.98% classification accuracy. A fully custom layout is developed to validate the design in a TSMC 180nm process. The area and power footprints of the spatial pooler are 30.538mm2 and 5.171mW, respectively. Storage processor units have the potential to be viable platforms to support implementations of HTM at scale

Algorithm Engineering for fundamental Sorting and Graph Problems

Fundamental Algorithms build a basis knowledge for every computer science undergraduate or a professional programmer. It is a set of basic techniques one can find in any (good) coursebook on algorithms and data structures. In this thesis we try to close the gap between theoretically worst-case optimal classical algorithms and the real-world circumstances one face under the assumptions imposed by the data size, limited main memory or available parallelism

Discrimination without awareness in a psychophysical task

Thesis (Ph.D.)--Boston University.Discrimination without awareness of the stimuli being responded to has been observed in a number of different experimental situations. In the classic case, the subject is instructed to relax or to engage in what is essentially a task of imagination, while incidental stimulation is presented at a level of intensity or duration such that he remains unaware of its presence. Responses of some comparatively unrestricted type are collected and analyzed for effects attributable to the stimulation. Present interest is in the case where the subject is effortfully attending to an objective task of discrimination. His range of possible responses to the task is quite narrow, and he is required to respond almost at once. The incidentally supplied stimulation is of a novel class, different from the stimulus material of the attended task; it is such as to present directly one of the possible task responses. The method used was an adaptation of a psychophysical judgment procedure, with individual subjects viewing the materials in a tachistoscope. A rectangular patch of standard size was presented first, followed in a few seconds by a test patch of variable size; the subject was required to report whether the latter was greater or smaller than the standard. A brief, unnoticed flash preceding the test patch carried the word greater or smaller or a nonsense control stimulus. A first experiment, using only three subjects, failed to yield any evidence of influence upon the judgments due to the unnoticed incidental words. In the second experiment, 32 subjects participated. The duration of the incidental flash waa gradually increased until the subject reported noticing its presence. Statistical analysis was restricted to the last 40 responses obtained at duration levels lower than the level at which recognition occurred. For the test patch of the same size as the standard (which had been presented on 24 of the 40 trials), it was clear that some subjects had indeed been influenced in the direction of agreeing with the unnoticed greater or smaller. The effect was statistically significant over all 32 subjects. About ten achieved a high degree of agreement with the incidental word, while the agreement scores of the others were distributed in approximately a chance fashion. Agreement was not influenced by sex of the subject. Four other test patches were of sizes greater or smaller than the standard. For two of these patches, subjects responded more accurately following the appropriate flash of greater or smaller than following the nonsense flash. No consistent relationships were found between latency of responding and agreement with the flashed stimulus. It is concluded from the main result that attended judgments of objective matters are (among some individuals) subject to influence from unreportable stimulation which directly presents the response to be used. This implies some necessary modification or extension of remarks made by Klein and others relative to this point. While attention usually acts to exclude activations which would be consciously rejected as inappropriate, such activations do (among some individuals) in a significant number of cases influence attended behavior without becoming conscious. A tentative conceptualization of the process is presented, based on psychoanalytic considerations by Kris and Fisher

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings