Hot electron injection laser : variable carrier heating for high-speed, low-chirp direct modulation

The novel Hot Electron Injection Laser (HEL), a three-terminal vertically integrated transistorlaser structure, is designed to investigate and possibly utilize the effects of carrier heating on the optical gain and wavelength chirp. Simulations show the potential of carrier heating assisted gain switching to directly modulate the optical field intensity at frequencies up to 100Ghz while minimizing the parasitic wavelength chirp. The HEL is designed to demonstrate these results through independent but complementary control over both the concentration and the energy of the electrons injected into the active layer. It utilizes a strong electric field to accelerate the electrons and distributes their energy inside the active layer. There the energy is used to modulate the material gain and to control the wavelength chirp. The electrons are heated and cooled by increasing or decreasing the energy of the injected carriers. Both the effectiveness of the launcher to increase the temperature of the electrons inside the active layer as well as the effect of higher electron temperatures on the material gain are investigated here. The Hot Electron Injection Laser derives its properties from the vertical integration of a diode laser with a heterojunction bipolar transistor. Joining the layer stacks of these devices puts extra emphasis on the epitaxial design to ensure proper transistor and laser behavior as well as the required electron heating. The epitaxial design rules are deduced and explained. Fabricating the Hot Electron Injection Laser involves the actual epitaxial growth of the designed layer stack and the subsequent characterization of these layers. It also involves transferring the patterns of the mask design onto the grown wafer. The three-terminal Hot Electron Injection Laser differs strongly from any conventional two-terminal diode laser in that it puts stronger requirements on the epitaxial layers and that it requires the additional base contact to control the base potential and thus the electric field across the launcher. And in spite of its narrow elongated design, the processing should still result in homogeneous carrier injection and a constant base potential along the cavity of the laser. The correct vertical integration of the transistor and the laser has proven to be the most challenging part of this thesis. The basic transistor current-voltage curves were measured first. The measurements continued by obtaining the optical properties like optical power versus current curves, threshold current densities and the optical spectrum. Finally these result were used to estimate the carrier heating efficiency. The measurement results indicate a certain level of heating voltage induced gain switching to be present. The possible effects on which that gain switching could be based are discussed and estimates for their relative contributions are given. The heating voltage induced carrier heating is within the range of carrier heating predicted by simulations based on the Monte Carlo method. Compensating for other possible electric field induced gain switching, such as the Electro-Optic or Pockels effect and the Franz-Keldysh effect, the remaining carrier heating induced gain switching is smaller than expected. Various improvements to the current implementation are discussed to increase the carrier heating induced gain switching

Transport models and advanced numerical simulation of silicon-germanium heterojunction bipolar transistors

Applications in the emerging high-frequency markets for millimeter wave applications more and more use SiGe components for cost reasons. To support the technology effort, a reliable TCAD platform is required. The main issue in the simulation of scaled devices is related to the limitations of the physical models used to describe charge carrier transport. Inherent approximations in the HD formalism are discussed over different technology nodes, providing for the first time a complete survey of HD models capability and restrictions with scaling for simulation of SiGe HBTs. Moreover, a complete set of models for transport parameters of SiGe HBTs is reported, including low-field mobility, energy relaxation time, saturation velocity, high-field mobility and effective density of state. Implementation in a commercial device simulator is drawn and findings are compared with simulation results obtained using a standard set of models and with trustworthy results (i.e. MC and SHE simulation results and experimental data), validating proposed models and clarifying their reliability and accuracy over different technologies. Finally, electrical breakdown phenomena in SiGe HBTs are analyzed: a novel complete model for multiplication factor is reported and validated by experimental results; new M model provides an exhaustive accuracy over a wide range of collector voltages

Design of III-Nitride Hot Electron Transistors

III-Nitride based devices have made great progress over the past few decades in electronics and photonics applications. As the technology and theoretical understanding of the III-N system matures, the limitations on further development are based on very basic electronic properties of the material, one of which is electron scattering (or ballistic electron effects). This thesis explores the design space of III-N based ballistic electron transistors using novel design, growth and process techniques. The hot electron transistor (HET) is a unipolar vertical device that operates on the principle of injecting electrons over a high-energy barrier (ϕBE) called the emitter into an n-doped region called base and finally collecting the high energy electrons (hot electrons) over another barrier (ϕBC) called the collector barrier. The injected electrons traverse the base in a quasi-ballistic manner. Electrons that get scattered in the base contribute to base current. High gain in the HET is thus achieved by enabling ballistic transport of electrons in the base. In addition, low leakage across the collector barrier (IBCleak) and low base resistance (RB) are needed to achieve high performance. Because of device attributes such as vertical structure, ballistic transport and low-resistance n-type base, the HET has the potential of operating at very high frequencies. Electrical measurements of a HET structure can be used to understand high-energy electron physics and extract information like mean free path in semiconductors. The III-Nitride material system is particularly suited for HETs as it offers a wide range of ΔEcs and polarization charges which can be engineered to obtain barriers which can inject hot-electrons and have low leakage at room temperature. In addition, polarization charges in the III-N system can be engineered to obtain a high-density and high-mobility 2DEG in the base, which can be used to reduce base resistance and allow vertical scaling. With these considerations in mind, III-N HETs had been explored in our research group earlier and gave us encouraging common base IV characteristics. Common emitter transistor operation was, however, not observed due to high RB and IBCleak. This thesis discusses several design and process challenges associated with the HET in general and specific to the III-N system. Many of these challenges like RB, IBCleak, and high energy injection were solved using novel combinations of hetero-structure and polarization engineering, device fabrication, and growth. Common-Emitter operation (with current gain ~ 0.1) was demonstrated in III-N HETs for the first time using injection and collector barriers induced by AlGaN and InGaN polarization-dipoles. In order to improve current gain, different parts of the III-N HET base which contribute to scattering, were identified. A novel base contact methodology using selective etching of GaN with respect to AlN was developed to enable base scaling. Aggressive scaling of all parts of the base was then used to increase current gain. A maximum gain of ~3.5 was demonstrated using a 1.5nm AlN layer as the emitter, 2nm GaN base and 2nm In0.2Ga0.8N as the collector P-D. This is the highest reported DC current gain in III-N HETs to date. The III-N HET structure was also used to extract the mean free path of hot-electrons (λmfp = 6nm) in GaN. The extracted value of mean free path has significant implications for any scaled devices which use ballistic or quasi-ballistic electron transport. We believe that the work presented in this dissertation provides a pathway for high gain in III-N HETs and eventual realization of their high frequency potential

Self-aligned gallium arsenide heterojunction bipolar transistor using refractory metallisation

Improvements in epitaxial growth and processing technologies have revived a great deal of interest in the heterojunction bipolar transistor (HBT). In this project, AIGaAs/GaAS HBTs have been fabricated using a new self-aligned process which exploits the characteristics of some refractory metals deposited by sputtering to obtain a T-shaped contact structure for the emitter. wet and dry etching techniques were used to fabricate the T-shaped contact. A refractory metallisation system consisting of sequentially sputtered layers of Ge/Mo/Ni was investigated for contacting the emitter of the transistor. After alloying in a thermal furnace at 750°C for 30 minutes in a nitrogen atmOSPhere, a low specific contact resistance of 2 x 10-6 ohm-cm was measured by standard transmission line model (TLM) for measurement of contact resistance. A metallisation system consisting of sequentially evaporated AU/Zn/Au was used for the base and Ni/AuGe/Ni/AU was used for the collector. Alloying with the same condition1 as above gave specific contact re1istances of 1.2 x 10-6 ohm-cm for the base and 8.6 x 10 -6 ohm-cm for the collector. AS an alternative to ion implantation, zinc diffusion was used as an alternative technique to dope the base contact region. The acceptor concentration profile of the diffused region was studied by 'Hall and Stripe' technique and a surface concentration of 1 x 10 20 cm -3 was measured. This highly doped base contact region can be used to achieve low ohmic contact to the base. Results show that for devices designed with similar dimensions for both processes, the new self-aligned process shows a net improvement in the frequency response of the devices (ft= 10.7GHZ and &nax=9.8GHZ for self-aligned and ft=8.0GHZ and for conventional 8um HBT)

DYNAMIC RANGE LIMITATIONS OF LOW-NOISE MICROWAVE TRANSISTORS AT CRYOGENIC TEMPERATURES

Dynamic range is an important metric that specifies the limits of input signal amplitude for the ideal operation of a given receiver. The low end of dynamic range is defined by the noise floor whereas the upper limit is determined by large-signal distortion. While dynamic range can be predicted in the temperature range where compact transistor models are valid, the lack of large-signal models at temperatures below -55 C prevents the prediction and optimization of dynamic range for applications that require cryogenic cooling. For decades, the main goal concerning the performance of these applications was lowering the noise floor of cryogenic receiver front-ends. For this, linear small-signal noise models have been extensively studied and used for designs of low-noise amplifiers. In this work, the existing small-signal noise modeling approach is extended to capture the weakly nonlinear properties of the transistors that are commonly used in cryogenic amplification. Indium phosphide high electron mobility transistors and silicon germanium heterojunction bipolar transistors are considered. The goal of this work is to identify the fundamental dynamic range limitations of these transistors such that the results are not device specific, but applicable to the corresponding device families. Identifying the fundamental limitations of dynamic range in a semiconductor device requires a broad understanding of physical properties of the transistors. For this, a theoretical analysis will be presented first as a function of temperature. The small-signal noise modeling will then be discussed using techniques that are well recognized in the literature. This will be followed by an explanation of the nonlinear modeling approach used in this work. This approach relies on the definition of Taylor series expansion coefficients of the dominant nonlinear mechanisms of the transistors. The modeling results will be interpreted with respect to the initially presented theoretical framework. Finally, the dynamic range performance will be studied as a function of source and load terminations. In addition to this systematic approach to understanding the physical limitations of dynamic range, model to measurement agreement of broadband cryogenic amplifiers will also be presented which will verify the accuracy of the modeling approach