402 research outputs found

    An Exponential Lower Bound for Homogeneous Depth-5 Circuits over Finite Fields

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    In this paper, we show exponential lower bounds for the class of homogeneous depth-5 circuits over all small finite fields. More formally, we show that there is an explicit family {P_d} of polynomials in VNP, where P_d is of degree d in n = d^{O(1)} variables, such that over all finite fields GF(q), any homogeneous depth-5 circuit which computes P_d must have size at least exp(Omega_q(sqrt{d})). To the best of our knowledge, this is the first super-polynomial lower bound for this class for any non-binary field. Our proof builds up on the ideas developed on the way to proving lower bounds for homogeneous depth-4 circuits [Gupta et al., Fournier et al., Kayal et al., Kumar-Saraf] and for non-homogeneous depth-3 circuits over finite fields [Grigoriev-Karpinski, Grigoriev-Razborov]. Our key insight is to look at the space of shifted partial derivatives of a polynomial as a space of functions from GF(q)^n to GF(q) as opposed to looking at them as a space of formal polynomials and builds over a tighter analysis of the lower bound of Kumar and Saraf [Kumar-Saraf]

    A Near-Optimal Depth-Hierarchy Theorem for Small-Depth Multilinear Circuits

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    We study the size blow-up that is necessary to convert an algebraic circuit of product-depth Δ+1\Delta+1 to one of product-depth Δ\Delta in the multilinear setting. We show that for every positive Δ=Δ(n)=o(logn/loglogn),\Delta = \Delta(n) = o(\log n/\log \log n), there is an explicit multilinear polynomial P(Δ)P^{(\Delta)} on nn variables that can be computed by a multilinear formula of product-depth Δ+1\Delta+1 and size O(n)O(n), but not by any multilinear circuit of product-depth Δ\Delta and size less than exp(nΩ(1/Δ))\exp(n^{\Omega(1/\Delta)}). This result is tight up to the constant implicit in the double exponent for all Δ=o(logn/loglogn).\Delta = o(\log n/\log \log n). This strengthens a result of Raz and Yehudayoff (Computational Complexity 2009) who prove a quasipolynomial separation for constant-depth multilinear circuits, and a result of Kayal, Nair and Saha (STACS 2016) who give an exponential separation in the case Δ=1.\Delta = 1. Our separating examples may be viewed as algebraic analogues of variants of the Graph Reachability problem studied by Chen, Oliveira, Servedio and Tan (STOC 2016), who used them to prove lower bounds for constant-depth Boolean circuits

    Transformers Learn Shortcuts to Automata

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    Algorithmic reasoning requires capabilities which are most naturally understood through recurrent models of computation, like the Turing machine. However, Transformer models, while lacking recurrence, are able to perform such reasoning using far fewer layers than the number of reasoning steps. This raises the question: what solutions are learned by these shallow and non-recurrent models? We find that a low-depth Transformer can represent the computations of any finite-state automaton (thus, any bounded-memory algorithm), by hierarchically reparameterizing its recurrent dynamics. Our theoretical results characterize shortcut solutions, whereby a Transformer with o(T)o(T) layers can exactly replicate the computation of an automaton on an input sequence of length TT. We find that polynomial-sized O(logT)O(\log T)-depth solutions always exist; furthermore, O(1)O(1)-depth simulators are surprisingly common, and can be understood using tools from Krohn-Rhodes theory and circuit complexity. Empirically, we perform synthetic experiments by training Transformers to simulate a wide variety of automata, and show that shortcut solutions can be learned via standard training. We further investigate the brittleness of these solutions and propose potential mitigations

    Study of information transfer optimization for communication satellites

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    The results are presented of a study of source coding, modulation/channel coding, and systems techniques for application to teleconferencing over high data rate digital communication satellite links. Simultaneous transmission of video, voice, data, and/or graphics is possible in various teleconferencing modes and one-way, two-way, and broadcast modes are considered. A satellite channel model including filters, limiter, a TWT, detectors, and an optimized equalizer is treated in detail. A complete analysis is presented for one set of system assumptions which exclude nonlinear gain and phase distortion in the TWT. Modulation, demodulation, and channel coding are considered, based on an additive white Gaussian noise channel model which is an idealization of an equalized channel. Source coding with emphasis on video data compression is reviewed, and the experimental facility utilized to test promising techniques is fully described

    High-Density Solid-State Memory Devices and Technologies

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    This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

    A mathematical model for predicting classification performance in wet fine screens

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    Screening is a well-known classification process in the minerals processing industry. The process involves separation of fine particles from coarse particles based on size and is applicable to both dry and fine screening. Fine screening is normally carried out wet. Until recently, fine wet screening had been limited to relatively low throughput applications. Developments in the recent past have seen the evolution of fine screening to high capacity applications. It has found application in operations such as closed circuits with a mill in place of hydrocyclones. However, even though developments are increasing, there has been a process model developmental lag. A fine wet screen model that can be used for unit simulation purposes to predict screen performance outcomes or integration into other models to simulate and predict process performance is necessary. Most existing screen models are for dry and coarse screening applications. This thesis is aimed at developing a fine wet screen process model for predicting wet screening performance in the 45 - 150 μm range. Pilot plant testwork was conducted using a UG2-Chrome ore blend as feed

    Methods for the atomistic simulation of ultrasmall semiconductor devices

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    As the feature sizes in VLSI technology shrink to less than 100 nm the effects due to the quantisation of electronic charge begin to emerge. There are a small number of carriers and impurities and the statistical variation in their number have significant effects on the threshold characteristics of the devices that hamper their large scale integration into future ULSI.The complex potential landscape arising from the Coulomb force, with its sharp localised peaks and troughs, faces problems due to band limiting in meshes and places heavy burdens on the integration techniques. A computationally efficient solution to the problem of band-limiting is presented and is shown to provide an accurate description of the electrostatics. This work also introduces a highly efficient and numerically stable multigrid solver, for Poisson's equation, that can cope with the complex potential distributions on large meshes.The study of ionised impurity scattering is used to validate these molecular dynamics simulations. Results have shown that the Brownian method - despite precluding the use of adaptive integration schemes - gives a good approximation to the standard results and has the advantage of smoothing away errors that can build up during the integration of motion and drives the system towards thermal equilibrium.The greatest hurdle to be cleared before these three-dimensional simulations can be practicable is the sheer computational effort that is required. The implementation of the problem on parallel architectures has been explored and discussed.The methods developed in this work are demonstrated through the simulation of an 80 nm dual-gate MESFET. The results were verified by comparing them with those from a commercial drift-diffusion simulator.The threshold behaviour of devices has been investigated through the study of the formation of conduction channels in blocks. The percolation threshold gives the point when conductive paths form across the gate barrier. The results from the FET simulation were found to be in agreement with the earlier studies on the blocks
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