Functionality in Design Protection Systems

In comparison to functionality doctrine in trade dress cases, scholars have paid relatively little attention to the role of functionality doctrine in design protection systems such as the U.S. design patent system and the EU Community Design regime. Yet functionality considerations potentially affect many validity and scope determinations in the design protection area. In this Article, we critically evaluate judicial application of the functionality doctrine in design protection systems, focusing on the U.S. design patent and EU design protection regimes. We argue that the doctrine as applied in these settings is too often aimless and inconsistent. Some simple doctrinal refinements would help, particularly in the U.S., where the Federal Circuit should definitively adopt the “dictated by” standard and should distinguish explicitly between functionality for invalidity purposes and functionality for scope purposes. Ultimately, a more carefully-considered theoretical justification for the functionality doctrine in design protection systems is needed, one that recognizes that trade dress functionality and design protection functionality serve different goals

Fashion\u27s Brand Heritage, Cultural Heritage, and the Piracy Paradox

This Article explores the role that heritage has on our understanding of the appropriateness of intellectual property protection for fashion designs in light of Christopher Sprigman and Kal Raustiala’s seminal work in The Piracy Paradox. At times, heritage seems to both reinforce Sprigman and Raustiala’s argument that fashion thrives in a low-IP regime and, at other times, heritage challenges that argument. Taking Italian fashion design as a case study, this Article considers the intersection of brand heritage, cultural heritage, and intellectual property law and makes three central observations. First, that fashion designs reflecting brand heritage thrive in a low-IP regime. Second, that fashion designs might only benefit from a higher-IP regime in instances where we understand fashion designs not as brand heritage alone, but as part of a wider cultural heritage. Finally, understanding the relationship between copyright law and cultural heritage law is central to exploring how a higher-IP regime might benefit fashion designs today

Modeling of a hardware VLSI placement system: Accelerating the Simulated Annealing algorithm

An essential step in the automation of electronic design is the placement of the physical components on the target semiconductor die. The placement step presents the opportunity to reduce costs in terms of wire length and performance degradation; however it is compute intensive and is NP-complete in terms of obtaining an optimal solution. As designs have grown in complexity and gate count, obtaining an optimal solution is not feasible due to time to market constraints or sheer compute effort required. Heuristic algorithms allow for efficient but sub-optimal designs to be produced with a reduction in processing time. A widely used algorithm is Simulated Annealing (SA). The goal of this work was to develop a model that would enable an analysis into the feasibility of developing a hardware accelerated placement system which uses SA at its core. The SA heuristic was analyzed for possible improvements in efficiency with focus given to targeting the system for hardware. A solution implementing parallel computing with specialized hardware configurations inside a field programmable gate array (FPGA) was investigated as having the possibility to improve the efficiency of the SA-based algorithm. All supporting subsystems were also described for a hardware accelerated model. A large speedup was analytically shown from both accelerating the critical path of the SA algorithm as well as novel methods of improving SA\u27s efficiency. As data throughput requirements were not included in this work, the results presented may be optimistic for an overall system speedup. However, the results clearly show that future work is warranted in studying the concept of a hardware accelerated placement system