679 research outputs found

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

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    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

    A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

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    The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

    Thermal stability analysis and performance exploration of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET for high performance circuit applications

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    This paper explores the performance of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET (device-D1) over the wide temperature range (200 K-450 K). An attempt has been made to find out the zero temperature coefficient (ZTC) biased point to enhance the digital, analog and RF performance at 20 nm channel length. The proposed device will be suitable for VLSI circuit’s design, internet of things (IoT) interfacing components and algorithm development for security applications of information technology. The potential parameters of device-D1 like intrinsic gain (AV ), output conductance (gd ), transconductance (gm ), early voltage (VEA ), off current (Ioff) , on current (Ion), Ion/Ioff ratio, gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), energy (CV2), intrinsic delay (CV/I), energy-delay product (EDP), power dissipation (PD), sub-threshold slope (SS), Q-Factor (gm,max/SS), threshold voltage (Vth) and maximum trans-conductance (gm,max) are subjected to analyze for evaluating the performance of ADKUS SOI FinFET for wide temperature environment. The validation of a temperature based performance of ADKUS SOI FinFET gives an opportunity to design the numerous analog and digital components of internet security infrastructure at wide temperature environment. These ADKUS SOI FinFET based components give new technology to the IoT which has the ability to connect the real world with the digital world and enables the people and machines to know the status of thousands of components simultaneously

    Design, Modeling and Analysis of Non-classical Field Effect Transistors

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    Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

    Multi-gate FinFET Mixer Variability assessment through physics-based simulation

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    In this paper we show that innovative physics-based simulations can be used for a comprehensive analysis of RF stages subject to random variations of technological parameters, including the computation of the average (deterministic) RF performance along with their statistical deviation. The variability analysis is addressed by means of the recently developed physicsbased sensitivity analysis of AC parameters through Green’s functions [1], [2]. To demonstrate the technique, we address the analysis of a FinFET mixer exploiting an innovative Independent Gates topology, showing that a careful design allows to maximize the mixer conversion gain while minimizing its variability vs. several physical parameters, such as the gate length, oxide thickness and fin width

    INFLUENCE OF OXIDE THICKNESS VARIATION ON ANALOG AND RF PERFORMANCES OF SOI FINFET

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    This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases

    TFET-Based power management circuit for RF energy harvesting

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    This paper proposes a Tunnel FET (TFET)-based power management circuit (PMC) for ultra-low power RF energy harvesting applications. In contrast with conventional thermionic devices, the band-to-band tunneling mechanism of TFETs allows a better switching performance at sub-0.2 V operation. As a result, improved efficiencies in RF-powered circuits are achieved, thanks to increased rectification performance at low power levels and to the reduced energy required for a proper PMC operation. It is shown by simulations that heterojunction TFET devices designed with III-V materials can improve the rectification process at received power levels below -20 dBm (915 MHz) when compared to the application of homojunction III-V TFETs and Si FinFETs. For an available power of -25 dBm, the proposed converter is able to deliver 1.1 µW of average power (with 0.5 V) to the output load with a boost efficiency of 86%.Postprint (author's final draft

    Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

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    IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT
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