Power Amplifiers Linearization Based On Complex Gain Memory Predistortion

Power Amplifiers (PAs) are important components in communication systems and are nonlinear. The nonlinearity creates out of band distortion beyond the signal bandwidth, which interferes with adjacent channels. It also causes distortions within the signal bandwidth, which decreases the bit error rate at the receiver. Digital predistortion is one of the most cost effective ways among all linearization techniques to compensate for these nonlinearities. In this thesis a novel technique for compensating memory effects and out of band distortions is proposed and is called Complex Gain Memory Predistortion (CGMP). The main advantage of the CGMP technique as compared to the memory polynomial technique is the ability of this technique to compensate all the memory effects inside the PA. Two structures of the CGMP technique are proposed. The CGMP technique is examined using two approaches, simulation and experiment. Power amplifiers are modeled with memory polynomial technique to examine the effects of the memory that causes increment in Adjacent Channel Leakage Ratio (ACLR). To implement this method, the complex divider is required. This complex divider is then designed and implemented in Field Programmable Gate Array (FPGA) and combined with other parts to make the predistortion block. The CGMP is implemented in Virtex 5 FPGA and simulated using Xilinx blocks in Matlab. In the experimental approach the CGMP is examined with the actual power amplifier ZVE-8G from Mini Circuit. Finally the CGMP technique is compared with memory polynomial method and validated using a 1.9 GHz 60W LDMOS power amplifier that is designed in simulation and various signals such as 2-carrier WCDMA with 10 MHz carrier spacing and Mobile WiMAX with 10 MHz bandwidth. The simulations results showed between 25 to 30 dB improvement in ACLR and almost 5 dB improvement as compared to the memory polynomial method. The experimental results also show around 10 dB reduction in ACLR with applying QPSK signal with 1 MHz bandwidth. The improvement of 7 percent in Power Added Efficiency (PAE) is also achieved

Independent digital predistortion parameters estimation using adaptive principal component analysis

©2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents an estimation/adaptation method based on the adaptive principal component analysis (APCA) technique to guarantee the identification of the minimum necessary parameters of a digital predistorter. The proposed estimation/adaptation technique is suitable for online field-programmable gate array or system on chip implementation. By exploiting the orthogonality of the resulting transformed matrix obtained with the APCA technique, it is possible to reduce the number of coefficients to be estimated which, at the same time, has a beneficial regularization effect by preventing ill-conditioning or overfitting problems. Therefore, this identification/adaptation method enhances the robustness of the parameter estimation and simplifies the adaptation by reducing the number of estimated coefficients. Due to the orthogonality of the new basis, these parameters can be estimated independently, thus allowing for scalability. Experimental results will show that it is possible to determine the minimum number of parameters to be estimated in order to meet the targeted linearity levels while ensuring a robust well-conditioned identification. Moreover, the results will show how thanks to the orthogonality property of the new basis functions, the coefficients of the digital predistorter can be estimated independently. This allows to tradeoff the digital predistorter adaptation time versus performance and hardware complexity.Peer ReviewedPostprint (author's final draft

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Optimization Of 5.7 Ghz Class E Power Amplifier For The Application Of Envelope Elimination And Restoration

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Rekabetin yoğun olduğu günümüzde tasarımcılar hafif, boyutları daha küçük ve düşük güçle çalışan yüksek performanslı ürün geliştirmenin yollarını aramaktadırlar. RF alıcı uygulamalarında güç kuvvetlendiricileri en fazla güç sarfiyatının olduğu bölümdür. Kablosuz iletişim sistemlerinde güç küvvetlendiricisi verimi maliyeti direkt olarak etkilemektedir. Teorik olarak %100 verim elde edilebilen E-sınıfı güç kuvvetlendiricileri transistorların açık/kapalı durum geçişlerinde güç sarfiyatını minimize edebilmektedir. Ayrıca çıkış gerilimi kaynak gerilimi ile doğrusal değişmektedir. Bu çalışmada E sınıfı güç kuvvetlendiricilerinin tasarım metodları ele alınmıştır. 5.7 GHz de çalışan birinde toplu devre elemanları, diğerinde transmisyon hattı elemanları kullanımış E sınıfı güç kuvvetlendiricileri tasarlanmıştır. Her iki devrede de %50 güç ekli verim (GEV) ve 500mW çıkış gücü elde edilmiştir. Sinyaldeki bozulmayı azaltmak için başvurulan doğrusallaştırma yöntemi Zarf Yoketme ve Tekrar Oluşturma metodudur. E sınıfı kuvvetlendiricinin Zarf Yoketme ve Tekrar Oluşturma yöntemi kullanılarak doğrusallaştırılmasıyla IMD bileşenlerinde 7.5 dB azalmış olup seviyesi gerçek işaretin 20dB altındadır.In today’s competitive, manufactures and product developers are seeking ways to build high performance devices that are lighter in weight, smaller in size and operating at lower power. In transceiver applications one module is responsible for a large portion of the power consumption - the power amplifier. The efficiency of the power amplifier has a direct impact on the cost of the wireless communication system. The class-E amplifier has a maximum theoretical efficiency of 100%. Class E power amplifiers have the ability to minimize power loss during on/off transitions of the transistor. Also, the output voltage varies linearly with the supply voltage. This thesis describes the design and the linearization methodology of the Class E amplifiers. Two class-E amplifiers operating at 5.7 GHz are presented. One of them is a lumped elements based circuit and the other is a transmission lines based circuit. Both circuit show good performance with 50% PAE and have 500mW output power. Envelope elimination and restoration is the linearization method chosen to achieve reduction of signal distortion. Linearization Class E PA using EER system provides an additional 7.5 dB reduction in intermodulation distortion products, achieving a minimum distortion level of 20 dB below the fundamental signals.Yüksek LisansM.Sc