On FPGA implementations for bioinformatics, neural prosthetics and reinforcement learning problems.

Mak Sui Tung Terrence.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 132-142).Abstracts in English and Chinese.Abstract --- p.iList of Tables --- p.ivList of Figures --- p.vAcknowledgements --- p.ixChapter 1. --- Introduction --- p.1Chapter 1.1 --- Bioinformatics --- p.1Chapter 1.2 --- Neural Prosthetics --- p.4Chapter 1.3 --- Learning in Uncertainty --- p.5Chapter 1.4 --- The Field Programmable Gate Array (FPGAs) --- p.7Chapter 1.5 --- Scope of the Thesis --- p.10Chapter 2. --- A Hybrid GA-DP Approach for Searching Equivalence Sets --- p.14Chapter 2.1 --- Introduction --- p.16Chapter 2.2 --- Equivalence Set Criterion --- p.18Chapter 2.3 --- Genetic Algorithm and Dynamic Programming --- p.19Chapter 2.3.1 --- Genetic Algorithm Formulation --- p.20Chapter 2.3.2 --- Bounded Mutation --- p.21Chapter 2.3.3 --- Conditioned Crossover --- p.22Chapter 2.3.4 --- Implementation --- p.22Chapter 2.4 --- FPGAs Implementation of GA-DP --- p.24Chapter 2.4.1 --- System Overview --- p.25Chapter 2.4.2 --- Parallel Computation for Transitive Closure --- p.26Chapter 2.4.3 --- Genetic Operation Realization --- p.28Chapter 2.5 --- Discussion --- p.30Chapter 2.6 --- Limitation and Future Work --- p.33Chapter 2.7 --- Conclusion --- p.34Chapter 3. --- An FPGA-based Architecture for Maximum-Likelihood Phylogeny Evaluation --- p.35Chapter 3.1 --- Introduction --- p.36Chapter 3.2 --- Maximum-Likelihood Model --- p.39Chapter 3.3 --- Hardware Mapping for Pruning Algorithm --- p.41Chapter 3.3.1 --- Related Works --- p.41Chapter 3.3.2 --- Number Representation --- p.42Chapter 3.3.3 --- Binary Tree Representation --- p.43Chapter 3.3.4 --- Binary Tree Traversal --- p.45Chapter 3.3.5 --- Maximum-Likelihood Evaluation Algorithm --- p.46Chapter 3.4 --- System Architecture --- p.49Chapter 3.4.1 --- Transition Probability Unit --- p.50Chapter 3.4.2 --- State-Parallel Computation Unit --- p.51Chapter 3.4.3 --- Error Computation --- p.54Chapter 3.5 --- Discussion --- p.56Chapter 3.5.1 --- Hardware Resource Consumption --- p.56Chapter 3.5.2 --- Delay Evaluation --- p.57Chapter 3.6 --- Conclusion --- p.59Chapter 4. --- Field Programmable Gate Array Implementation of Neuronal Ion Channel Dynamics --- p.61Chapter 4.1 --- Introduction --- p.62Chapter 4.2 --- Background --- p.63Chapter 4.2.1 --- Analog VLSI Model for Hebbian Synapse --- p.63Chapter 4.2.2 --- A Unifying Model of Bi-directional Synaptic Plasticity --- p.64Chapter 4.2.3 --- Non-NMDA Receptor Channel Regulation --- p.65Chapter 4.3 --- FPGAs Implementation --- p.65Chapter 4.3.1 --- FPGA Design Flow --- p.65Chapter 4.3.2 --- Digital Model of NMD A and AMPA receptors --- p.65Chapter 4.3.3 --- Synapse Modification --- p.67Chapter 4.4 --- Results --- p.68Chapter 4.4.1 --- Simulation Results --- p.68Chapter 4.5 --- Discussion --- p.70Chapter 4.6 --- Conclusion --- p.71Chapter 5. --- Continuous-Time and Discrete-Time Inference Networks for Distributed Dynamic Programming --- p.72Chapter 5.1 --- Introduction --- p.74Chapter 5.2 --- Background --- p.77Chapter 5.2.1 --- Markov decision process (MDPs) --- p.78Chapter 5.2.2 --- Learning in the MDPs --- p.80Chapter 5.2.3 --- Bellman Optimal Criterion --- p.80Chapter 5.2.4 --- Value Iteration --- p.81Chapter 5.3 --- A Computational Framework for Continuous-Time Inference Network --- p.82Chapter 5.3.1 --- Binary Relation Inference Network --- p.83Chapter 5.3.2 --- Binary Relation Inference Network for MDPs --- p.85Chapter 5.3.3 --- Continuous-Time Inference Network for MDPs --- p.87Chapter 5.4 --- Convergence Consideration --- p.88Chapter 5.5 --- Numerical Simulation --- p.90Chapter 5.5.1 --- Example 1: Random Walk --- p.90Chapter 5.5.2 --- Example 2: Random Walk on a Grid --- p.94Chapter 5.5.3 --- Example 3: Stochastic Shortest Path Problem --- p.97Chapter 5.5.4 --- Relationships Between λ and γ --- p.99Chapter 5.6 --- Discrete-Time Inference Network --- p.100Chapter 5.6.1 --- Results --- p.101Chapter 5.7 --- Conclusion --- p.102Chapter 6. --- On Distributed g-Learning Network --- p.104Chapter 6.1 --- Introduction --- p.105Chapter 6.2 --- Distributed Q-Learniing Network --- p.108Chapter 6.2.1 --- Distributed Q-Learning Network --- p.109Chapter 6.2.2 --- Q-Learning Network Architecture --- p.111Chapter 6.3 --- Experimental Results --- p.114Chapter 6.3.1 --- Random Walk --- p.114Chapter 6.3.2 --- The Shortest Path Problem --- p.116Chapter 6.4 --- Discussion --- p.120Chapter 6.4.1 --- Related Work --- p.121Chapter 6.5 --- FPGAs Implementation --- p.122Chapter 6.5.1 --- Distributed Registering Approach --- p.123Chapter 6.5.2 --- Serial BRAM Storing Approach --- p.124Chapter 6.5.3 --- Comparison --- p.125Chapter 6.5.4 --- Discussion --- p.127Chapter 6.6 --- Conclusion --- p.128Chapter 7. --- Summary --- p.129Bibliography --- p.132AppendixChapter A. --- Simplified Floating-Point Arithmetic --- p.143Chapter B. --- "Logarithm, Exponential and Division Implementation" --- p.144Chapter B.1 --- Introduction --- p.144Chapter B.2 --- Approximation Scheme --- p.145Chapter B.2.1 --- Logarithm --- p.145Chapter B.2.2 --- Exponentiation --- p.147Chapter B.2.3 --- Division --- p.148Chapter C. --- Analog VLSI Implementation --- p.150Chapter C.1 --- Site Function --- p.150Chapter C.1.1 --- Multiplication Cell --- p.150Chapter C.2 --- The Unit Function --- p.153Chapter C.3 --- The Inference Network Computation --- p.154Chapter C.4 --- Layout --- p.157Chapter C.5 --- Fabrication --- p.159Chapter C.5.1 --- Testing and Characterization --- p.16

Analog Photonics Computing for Information Processing, Inference and Optimisation

This review presents an overview of the current state-of-the-art in photonics computing, which leverages photons, photons coupled with matter, and optics-related technologies for effective and efficient computational purposes. It covers the history and development of photonics computing and modern analogue computing platforms and architectures, focusing on optimization tasks and neural network implementations. The authors examine special-purpose optimizers, mathematical descriptions of photonics optimizers, and their various interconnections. Disparate applications are discussed, including direct encoding, logistics, finance, phase retrieval, machine learning, neural networks, probabilistic graphical models, and image processing, among many others. The main directions of technological advancement and associated challenges in photonics computing are explored, along with an assessment of its efficiency. Finally, the paper discusses prospects and the field of optical quantum computing, providing insights into the potential applications of this technology.Comment: Invited submission by Journal of Advanced Quantum Technologies; accepted version 5/06/202

Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces

High-density microelectrode arrays (HDMEAs) feature thousands of recording electrodes in a single chip with an area of few square millimeters. The obtained electrode density is comparable and even higher than the typical density of neuronal cells in cortical cultures. Commercially available HDMEA-based acquisition systems are able to record the neural activity from the whole array at the same time with submillisecond resolution. These devices are a very promising tool and are increasingly used in neuroscience to tackle fundamental questions regarding the complex dynamics of neural networks. Even if electrical or optical stimulation is generally an available feature of such systems, they lack the capability of creating a closed-loop between the biological neural activity and the artificial system. Stimuli are usually sent in an open-loop manner, thus violating the inherent working basis of neural circuits that in nature are constantly reacting to the external environment. This forbids to unravel the real mechanisms behind the behavior of neural networks. The primary objective of this PhD work is to overcome such limitation by creating a fullyreconfigurable processing system capable of providing real-time feedback to the ongoing neural activity recorded with HDMEA platforms. The potentiality of modern heterogeneous FPGAs has been exploited to realize the system. In particular, the Xilinx Zynq All Programmable System on Chip (APSoC) has been used. The device features reconfigurable logic, specialized hardwired blocks, and a dual-core ARM-based processor; the synergy of these components allows to achieve high elaboration performances while maintaining a high level of flexibility and adaptivity. The developed system has been embedded in an acquisition and stimulation setup featuring the following platforms: \u2022 3\ub7Brain BioCam X, a state-of-the-art HDMEA-based acquisition platform capable of recording in parallel from 4096 electrodes at 18 kHz per electrode. \u2022 PlexStim\u2122 Electrical Stimulator System, able to generate electrical stimuli with custom waveforms to 16 different output channels. \u2022 Texas Instruments DLP\uae LightCrafter\u2122 Evaluation Module, capable of projecting 608x684 pixels images with a refresh rate of 60 Hz; it holds the function of optical stimulation. All the features of the system, such as band-pass filtering and spike detection of all the recorded channels, have been validated by means of ex vivo experiments. Very low-latency has been achieved while processing the whole input data stream in real-time. In the case of electrical stimulation the total latency is below 2 ms; when optical stimuli are needed, instead, the total latency is a little higher, being 21 ms in the worst case. The final setup is ready to be used to infer cellular properties by means of closed-loop experiments. As a proof of this concept, it has been successfully used for the clustering and classification of retinal ganglion cells (RGCs) in mice retina. For this experiment, the light-evoked spikes from thousands of RGCs have been correctly recorded and analyzed in real-time. Around 90% of the total clusters have been classified as ON- or OFF-type cells. In addition to the closed-loop system, a denoising prototype has been developed. The main idea is to exploit oversampling techniques to reduce the thermal noise recorded by HDMEAbased acquisition systems. The prototype is capable of processing in real-time all the input signals from the BioCam X, and it is currently being tested to evaluate the performance in terms of signal-to-noise-ratio improvement

Applications and implementation of neuro-connectionist architectures.

by H.S. Ng.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references (leaves 91-97).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Introduction --- p.1Chapter 1.2 --- Neuro-connectionist Network --- p.2Chapter 2 --- Related Works --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.1.1 --- Kruskal's Algorithm --- p.5Chapter 2.1.2 --- Prim's algorithm --- p.6Chapter 2.1.3 --- Sollin's algorithm --- p.7Chapter 2.1.4 --- Bellman-Ford algorithm --- p.8Chapter 2.1.5 --- Floyd-Warshall algorithm --- p.9Chapter 3 --- Binary Relation Inference Network and Path Problems --- p.11Chapter 3.1 --- Introduction --- p.11Chapter 3.2 --- Topology --- p.12Chapter 3.3 --- Network structure --- p.13Chapter 3.3.1 --- Single-destination BRIN architecture --- p.14Chapter 3.3.2 --- Comparison between all-pair BRIN and single-destination BRIN --- p.18Chapter 3.4 --- Path Problems and BRIN Solution --- p.18Chapter 3.4.1 --- Minimax path problems --- p.18Chapter 3.4.2 --- BRIN solution --- p.19Chapter 4 --- Analog and Voltage-mode Approach --- p.22Chapter 4.1 --- Introduction --- p.22Chapter 4.2 --- Analog implementation --- p.24Chapter 4.3 --- Voltage-mode approach --- p.26Chapter 4.3.1 --- The site function --- p.26Chapter 4.3.2 --- The unit function --- p.28Chapter 4.3.3 --- The computational unit --- p.28Chapter 4.4 --- Conclusion --- p.29Chapter 5 --- Current-mode Approach --- p.32Chapter 5.1 --- Introduction --- p.32Chapter 5.2 --- Current-mode approach for analog VLSI Implementation --- p.33Chapter 5.2.1 --- Site and Unit output function --- p.33Chapter 5.2.2 --- Computational unit --- p.34Chapter 5.2.3 --- A complete network --- p.35Chapter 5.3 --- Conclusion --- p.37Chapter 6 --- Neural Network Compensation for Optimization Circuit --- p.40Chapter 6.1 --- Introduction --- p.40Chapter 6.2 --- A Neuro-connectionist Architecture for error correction --- p.41Chapter 6.2.1 --- Linear Relationship --- p.42Chapter 6.2.2 --- Output Deviation of Computational Unit --- p.44Chapter 6.3 --- Experimental Results --- p.46Chapter 6.3.1 --- Training Phase --- p.46Chapter 6.3.2 --- Generalization Phase --- p.48Chapter 6.4 --- Conclusion --- p.50Chapter 7 --- Precision-limited Analog Neural Network Compensation --- p.51Chapter 7.1 --- Introduction --- p.51Chapter 7.2 --- Analog Neural Network hardware --- p.53Chapter 7.3 --- Integration of analog neural network compensation of connectionist net- work for general path problems --- p.54Chapter 7.4 --- Experimental Results --- p.55Chapter 7.4.1 --- Convergence time --- p.56Chapter 7.4.2 --- The accuracy of the system --- p.57Chapter 7.5 --- Conclusion --- p.58Chapter 8 --- Transitive Closure Problems --- p.60Chapter 8.1 --- Introduction --- p.60Chapter 8.2 --- Different ways of implementation of BRIN for transitive closure --- p.61Chapter 8.2.1 --- Digital Implementation --- p.61Chapter 8.2.2 --- Analog Implementation --- p.61Chapter 8.3 --- Transitive Closure Problem --- p.63Chapter 8.3.1 --- A special case of maximum spanning tree problem --- p.64Chapter 8.3.2 --- Analog approach solution for transitive closure problem --- p.65Chapter 8.3.3 --- Current-mode approach solution for transitive closure problem --- p.67Chapter 8.4 --- Comparisons between the different forms of implementation of BRIN for transitive closure --- p.71Chapter 8.4.1 --- Convergence Time --- p.71Chapter 8.4.2 --- Circuit complexity --- p.72Chapter 8.5 --- Discussion --- p.73Chapter 9 --- Critical path problems --- p.74Chapter 9.1 --- Introduction --- p.74Chapter 9.2 --- Problem statement and single-destination BRIN solution --- p.75Chapter 9.3 --- Analog implementation --- p.76Chapter 9.3.1 --- Separated building block --- p.78Chapter 9.3.2 --- Combined building block --- p.79Chapter 9.4 --- Current-mode approach --- p.80Chapter 9.4.1 --- "Site function, unit output function and a completed network" --- p.80Chapter 9.5 --- Conclusion --- p.83Chapter 10 --- Conclusions --- p.85Chapter 10.1 --- Summary of Achievements --- p.85Chapter 10.2 --- Future development --- p.88Chapter 10.2.1 --- Application for financial problems --- p.88Chapter 10.2.2 --- Fabrication of VLSI Implementation --- p.88Chapter 10.2.3 --- Actual prototyping of Analog Integrated Circuits for critical path and transitive closure problems --- p.89Chapter 10.2.4 --- Other implementation platform --- p.89Chapter 10.2.5 --- On-line update of routing table inside the router for network com- munication using BRIN --- p.89Chapter 10.2.6 --- Other BRIN's applications --- p.90Bibliography --- p.9

Applications and implementation of neuro-connectionist architectures.

by H.S. Ng.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references (leaves 91-97).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Introduction --- p.1Chapter 1.2 --- Neuro-connectionist Network --- p.2Chapter 2 --- Related Works --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.1.1 --- Kruskal's Algorithm --- p.5Chapter 2.1.2 --- Prim's algorithm --- p.6Chapter 2.1.3 --- Sollin's algorithm --- p.7Chapter 2.1.4 --- Bellman-Ford algorithm --- p.8Chapter 2.1.5 --- Floyd-Warshall algorithm --- p.9Chapter 3 --- Binary Relation Inference Network and Path Problems --- p.11Chapter 3.1 --- Introduction --- p.11Chapter 3.2 --- Topology --- p.12Chapter 3.3 --- Network structure --- p.13Chapter 3.3.1 --- Single-destination BRIN architecture --- p.14Chapter 3.3.2 --- Comparison between all-pair BRIN and single-destination BRIN --- p.18Chapter 3.4 --- Path Problems and BRIN Solution --- p.18Chapter 3.4.1 --- Minimax path problems --- p.18Chapter 3.4.2 --- BRIN solution --- p.19Chapter 4 --- Analog and Voltage-mode Approach --- p.22Chapter 4.1 --- Introduction --- p.22Chapter 4.2 --- Analog implementation --- p.24Chapter 4.3 --- Voltage-mode approach --- p.26Chapter 4.3.1 --- The site function --- p.26Chapter 4.3.2 --- The unit function --- p.28Chapter 4.3.3 --- The computational unit --- p.28Chapter 4.4 --- Conclusion --- p.29Chapter 5 --- Current-mode Approach --- p.32Chapter 5.1 --- Introduction --- p.32Chapter 5.2 --- Current-mode approach for analog VLSI Implementation --- p.33Chapter 5.2.1 --- Site and Unit output function --- p.33Chapter 5.2.2 --- Computational unit --- p.34Chapter 5.2.3 --- A complete network --- p.35Chapter 5.3 --- Conclusion --- p.37Chapter 6 --- Neural Network Compensation for Optimization Circuit --- p.40Chapter 6.1 --- Introduction --- p.40Chapter 6.2 --- A Neuro-connectionist Architecture for error correction --- p.41Chapter 6.2.1 --- Linear Relationship --- p.42Chapter 6.2.2 --- Output Deviation of Computational Unit --- p.44Chapter 6.3 --- Experimental Results --- p.46Chapter 6.3.1 --- Training Phase --- p.46Chapter 6.3.2 --- Generalization Phase --- p.48Chapter 6.4 --- Conclusion --- p.50Chapter 7 --- Precision-limited Analog Neural Network Compensation --- p.51Chapter 7.1 --- Introduction --- p.51Chapter 7.2 --- Analog Neural Network hardware --- p.53Chapter 7.3 --- Integration of analog neural network compensation of connectionist net- work for general path problems --- p.54Chapter 7.4 --- Experimental Results --- p.55Chapter 7.4.1 --- Convergence time --- p.56Chapter 7.4.2 --- The accuracy of the system --- p.57Chapter 7.5 --- Conclusion --- p.58Chapter 8 --- Transitive Closure Problems --- p.60Chapter 8.1 --- Introduction --- p.60Chapter 8.2 --- Different ways of implementation of BRIN for transitive closure --- p.61Chapter 8.2.1 --- Digital Implementation --- p.61Chapter 8.2.2 --- Analog Implementation --- p.61Chapter 8.3 --- Transitive Closure Problem --- p.63Chapter 8.3.1 --- A special case of maximum spanning tree problem --- p.64Chapter 8.3.2 --- Analog approach solution for transitive closure problem --- p.65Chapter 8.3.3 --- Current-mode approach solution for transitive closure problem --- p.67Chapter 8.4 --- Comparisons between the different forms of implementation of BRIN for transitive closure --- p.71Chapter 8.4.1 --- Convergence Time --- p.71Chapter 8.4.2 --- Circuit complexity --- p.72Chapter 8.5 --- Discussion --- p.73Chapter 9 --- Critical path problems --- p.74Chapter 9.1 --- Introduction --- p.74Chapter 9.2 --- Problem statement and single-destination BRIN solution --- p.75Chapter 9.3 --- Analog implementation --- p.76Chapter 9.3.1 --- Separated building block --- p.78Chapter 9.3.2 --- Combined building block --- p.79Chapter 9.4 --- Current-mode approach --- p.80Chapter 9.4.1 --- "Site function, unit output function and a completed network" --- p.80Chapter 9.5 --- Conclusion --- p.83Chapter 10 --- Conclusions --- p.85Chapter 10.1 --- Summary of Achievements --- p.85Chapter 10.2 --- Future development --- p.88Chapter 10.2.1 --- Application for financial problems --- p.88Chapter 10.2.2 --- Fabrication of VLSI Implementation --- p.88Chapter 10.2.3 --- Actual prototyping of Analog Integrated Circuits for critical path and transitive closure problems --- p.89Chapter 10.2.4 --- Other implementation platform --- p.89Chapter 10.2.5 --- On-line update of routing table inside the router for network com- munication using BRIN --- p.89Chapter 10.2.6 --- Other BRIN's applications --- p.90Bibliography --- p.9

Unconventional computing platforms and nature-inspired methods for solving hard optimisation problems

The search for novel hardware beyond the traditional von Neumann architecture has given rise to a modern area of unconventional computing requiring the efforts of mathematicians, physicists and engineers. Many analogue physical systems, including networks of nonlinear oscillators, lasers, condensates, and superconducting qubits, are proposed and realised to address challenging computational problems from various areas of social and physical sciences and technology. Understanding the underlying physical process by which the system finds the solutions to such problems often leads to new optimisation algorithms. This thesis focuses on studying gain-dissipative systems and nature-inspired algorithms that form a hybrid architecture that may soon rival classical hardware. Chapter 1 lays the necessary foundation and explains various interdisciplinary terms that are used throughout the dissertation. In particular, connections between the optimisation problems and spin Hamiltonians are established, their computational complexity classes are explained, and the most prominent physical platforms for spin Hamiltonian implementation are reviewed. Chapter 2 demonstrates a large variety of behaviours encapsulated in networks of polariton condensates, which are a vivid example of a gain-dissipative system we use throughout the thesis. We explain how the variations of experimentally tunable parameters allow the networks of polariton condensates to represent different oscillator models. We derive analytic expressions for the interactions between two spatially separated polariton condensates and show various synchronisation regimes for periodic chains of condensates. An odd number of condensates at the vertices of a regular polygon leads to a spontaneous formation of a giant multiply-quantised vortex at the centre of a polygon. Numerical simulations of all studied configurations of polariton condensates are performed with a mean-field approach with some theoretically proposed physical phenomena supported by the relevant experiments. Chapter 3 examines the potential of polariton graphs to find the low-energy minima of the spin Hamiltonians. By associating a spin with a condensate phase, the minima of the XY model are achieved for simple configurations of spatially-interacting polariton condensates. We argue that such implementation of gain-dissipative simulators limits their applicability to the classes of easily solvable problems since the parameters of a particular Hamiltonian depend on the node occupancies that are not known a priori. To overcome this difficulty, we propose to adjust pumping intensities and coupling strengths dynamically. We further theoretically suggest how the discrete Ising and $n$-state planar Potts models with or without external fields can be simulated using gain-dissipative platforms. The underlying operational principle originates from a combination of resonant and non-resonant pumping. Spatial anisotropy of pump and dissipation profiles enables an effective control of the sign and intensity of the coupling strength between any two neighbouring sites, which we demonstrate with a two dimensional square lattice of polariton condensates. For an accurate minimisation of discrete and continuous spin Hamiltonians, we propose a fully controllable polaritonic XY-Ising machine based on a network of geometrically isolated polariton condensates. In Chapter 4, we look at classical computing rivals and study nature-inspired methods for optimising spin Hamiltonians. Based on the operational principles of gain-dissipative machines, we develop a novel class of gain-dissipative algorithms for the optimisation of discrete and continuous problems and show its performance in comparison with traditional optimisation techniques. Besides looking at traditional heuristic methods for Ising minimisation, such as the Hopfield-Tank neural networks and parallel tempering, we consider a recent physics-inspired algorithm, namely chaotic amplitude control, and exact commercial solver, Gurobi. For a proper evaluation of physical simulators, we further discuss the importance of detecting easy instances of hard combinatorial optimisation problems. The Ising model for certain interaction matrices, that are commonly used for evaluating the performance of unconventional computing machines and assumed to be exponentially hard, is shown to be solvable in polynomial time including the Mobius ladder graphs and Mattis spin glasses. In Chapter 5 we discuss possible future applications of unconventional computing platforms including emulation of search algorithms such as PageRank, realisation of a proof-of-work protocol for blockchain technology, and reservoir computing

組合せ最適化問題のための測定フィードバック型コヒーレント・イジングマシンの実現と評価

学位の種別: 課程博士審査委員会委員 : （主査）東京大学教授 合原 一幸, 東京大学教授 岩田 覚, 東京大学准教授 平田 祥人, 東京大学准教授 大西 立顕, 東京大学准教授 鈴木 大慈University of Tokyo(東京大学

Hydrogel-based logic circuits for planar microfluidics and lab-on-a-chip automation

The transport of vital nutrient supply in fluids as well as the exchange of specific chemical signals from cell to cell has been optimized over billion years of natural evolution. This model from nature is a driving factor in the field of microfluidics, which investigates the manipulation of the smallest amounts of fluid with the aim of applying these effects in fluidic microsystems for technical solutions. Currently, microfluidic systems are receiving attention, especially in diagnostics, \textit{e.g.} as SARS-CoV-2 antigen tests, or in the field of high-throughput analysis, \textit{e.g.} for cancer research. Either simple-to-use or large-scale integrated microfluidic systems that perform biological and chemical laboratory investigations on a so called Lab-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents due to system miniaturization. Despite the great progress of different LoC technology platforms in the last 30 years, there is still a lack of standardized microfluidic components, as well as a high-performance, fully integrated on-chip automation. Quite promising for the microfluidic system design is the similarity of the Kirchhoff's laws from electronics to predict pressure and flow rate in microchannel structures. One specific LoC platform technology approach controls fluids by active polymers which respond to specific physical and chemical signals in the fluid. Analogue to (micro-)electronics, these active polymer materials can be realized by various photolithographic and micro patterning methods to generate functional elements at high scalability. The so called chemofluidic circuits have a high-functional potential and provide “real” on-chip automation, but are complex in system design. In this work, an advanced circuit concept for the planar microfluidic chip architecture, originating from the early era of the semiconductor-based resistor-transistor-logic (RTL) will be presented. Beginning with the state of the art of microfluidic technologies, materials, and methods of this work will be further described. Then the preferred fabrication technology is evaluated and various microfluidic components are discussed in function and design. The most important component to be characterized is the hydrogel-based chemical volume phase transition transistor (CVPT) which is the key to approach microfluidic logic gate operations. This circuit concept (CVPT-RTL) is robust and simple in design, feasible with common materials and manufacturing techniques. Finally, application scenarios for the CVPT-RTL concept are presented and further development recommendations are proposed.:1 The transistor: invention of the 20th century 2 Introduction to fluidic microsystems and the theoretical basics 2.1 Fluidic systems at the microscale 2.2 Overview of microfluidic chip fabrication 2.2.1 Common substrate materials for fluidic microsystems 2.2.2 Structuring polymer substrates for microfluidics 2.2.3 Polymer chip bonding technologies 2.3 Fundamentals and microfluidic transport processes 2.3.1 Fluid dynamics in miniaturized systems 2.3.2 Hagen-Poiseuille law: the fluidic resistance 2.3.3 Electronic and microfluidic circuit model analogy 2.3.4 Limits of the electro-fluidic analogy 2.4 Active components for microfluidic control 2.4.1 Fluid transport by integrated micropumps 2.4.2 Controlling fluids by on-chip microvalves 2.4.3 Hydrogel-based microvalve archetypes 2.5 LoC technologies: lost in translation? 2.6 Microfluidic platforms providing logic operations 2.6.1 Hybrids: MEMS-based logic concepts 2.6.2 Intrinsic logic operators for microfluidic circuits 2.7 Research objective: microfluidic hydrogel-based logic circuits 3 Stimuli-responsive polymers for microfluidics 3.1 Introduction to hydrogels 3.1.1 Application variety of hydrogels 3.1.2 Hydrogel microstructuring methods 3.2 Theory: stimuli-responsive hydrogels 3.3 PNIPAAm: a multi-responsive hydrogel 4 Design, production and characterization methods of hydrogel-based microfluidic systems 4.1 The semi-automated computer aided design approach for microfluidic systems 4.2 The applied design process 4.3 Fabrication of microfluidic chips 4.3.1 Photoresist master fabrication 4.3.2 Soft lithography for PDMS chip production 4.3.3 Assembling PDMS chips by plasma bonding 4.4 Integration of functional hydrogels in microfluidic chips 4.4.1 Preparation of a monomer solution for hydrogel synthesis 4.4.2 Integration methods 4.5 Effects on hydrogel photopolymerization and the role of integration method 4.5.1 Photopolymerization from monomer solutions: managing the diffusion of free radicals 4.5.2 Hydrogel adhesion and UV light intensity distribution in the polymerization chamber 4.5.3 Hydrogel shrinkage behavior of different adhesion types 4.6 Comparison of the integration methods 4.7 Characterization setups for hydrogel actuators and microfluidic measurements . 71 4.7.1 Optical characterization method to describe swelling behavior 4.7.2 Setup of a microfluidic test stand 4.8 Conclusion: design, production and characterization methods 5 VLSI technology for hydrogel-based microfluidics 5.1 Overview of photolithography methods 5.2 Standard UV photolithography system for microfluidic structures 5.3 Self-made UV lithography system suitable for the mVLSI 5.3.1 Lithography setup for the DFR and SU-8 master exposure 5.3.2 Comparison of mask-based UV induced crosslinking for DFR and SU-8 5.4 Mask-based UV photopolymerization for mVLSI hydrogel patterning 5.4.1 Lithography setup for the photopolymerization of hydrogels 5.4.2 Hydrogel photopolymerization: experiments and results 5.4.3 Troubleshooting: photopolymerization of hydrogels 5.5 Conclusion: mVLSI technologies for hydrogel-based LoCs 6 Components for chemofluidic circuit design 6.1 Passive components in microfluidics 6.1.1 Microfluidic resistor 6.1.2 Planar-passive microfluidic signal mixer 6.1.3 Phase separation: laminar flow signal splitter 6.1.4 Hydrogel-based microfluidic one-directional valves 6.2 Hydrogel-based active components 6.2.1 Reversible hydrogel-based valves 6.2.2 Hydrogel-based variable resistors 6.2.3 CVPT: the microfluidic transistor 6.3 Conclusion: components for chemofluidic circuits 7 Hydrogel-based logic circuits in planar microfluidics 7.1 Development of a planar CVPT logic concept 7.1.1 Challenges of planar microfluidics 7.1.2 Preparatory work and conceptional basis 7.2 The microfluidic CVPT-RTL concept 7.3 The CVPT-RTL NAND gate 7.3.1 Circuit optimization stabilizing the NAND operating mode 7.3.2 Role of laminar flow for the CVPT-RTL concept 7.3.3 Hydrogel-based components for improved switching reliability 7.4 One design fits all: the NOR, AND and OR gate 7.5 Control measures for cascaded systems 7.6 Application scenarios for the CVPT-RTL concept 7.6.1 Use case: automated cell growth system 7.6.2 Use case: chemofluidic converter 7.7 Conclusion: Hydrogel-based logic circuits 8 Summary and outlook 8.1 Scientific achievements 8.2 Summarized recommendations from this work Supplementary information SI.1 Swelling degree of BIS-pNIPAAm gels SI.2 Simulated ray tracing of UV lithography setup by WinLens® SI.3 Determination of the resolution using the intercept theorem SI.4 Microfluidic master mold test structures SI.4.1 Polymer and glass mask comparison SI.4.2 Resolution Siemens star in DFR SI.4.3 Resolution Siemens star in SU-8 SI.4.4 Integration test array 300 μm for DFR and SU-8 SI.4.5 Integration test array 100 μm for SU-8 SI.4.6 Microfluidic structure for different technology parameters SI.5 Microfluidic test setups SI.6 Supplementary information: microfluidic components SI.6.1 Compensation methods for flow stabilization in microfluidic chips SI.6.2 Planar-passive microfluidic signal mixer SI.6.3 Laminar flow signal splitter SI.6.4 Variable fluidic resistors: flow rate characteristics SI.6.5 CVPT flow rate characteristics for high Rout Standard operation proceduresDer Transport von lebenswichtigen Nährstoffen in Flüssigkeiten sowie der Austausch spezifischer chemischer Signale von Zelle zu Zelle wurde in Milliarden Jahren natürlicher Evolution optimiert. Dieses Vorbild aus der Natur ist ein treibender Faktor im Fachgebiet der Mikrofluidik, welches die Manipulation kleinster Flüssigkeitsmengen erforscht um diese Effekte in fluidischen Mikrosystemen für technische Lösungen zu nutzen. Derzeit finden mikrofluidische Systeme vor allem in der Diagnostik, z.B. wie SARS-CoV-2-Antigentests, oder im Bereich der Hochdurchsatzanalyse, z.B. in der Krebsforschung, besondere Beachtung. Entweder einfach zu bedienende oder hochintegrierte mikrofluidische Systeme, die biologische und chemische Laboruntersuchungen auf einem sogenannten Lab-on-a-Chip (LoC) durchführen, bieten schnelle Analysen, hohe Funktionalität, hervorragende Reproduzierbarkeit bei niedrigen Kosten pro Probe und einen geringen Bedarf an Reagenzien durch die Miniaturisierung des Systems. Trotz des großen Fortschritts verschiedener LoC-Technologieplattformen in den letzten 30 Jahren mangelt es noch an standardisierten mikrofluidischen Komponenten sowie an einer leistungsstarken, vollintegrierten On-Chip-Automatisierung. Vielversprechend für das Design mikrofluidischer Systeme ist die Ähnlichkeit der Kirchhoff'schen Gesetze aus der Elektronik zur Vorhersage von Druck und Flussrate in Mikrokanalstrukturen. Ein spezifischer Ansatz der LoC-Plattformtechnologie steuert Flüssigkeiten durch aktive Polymere, die auf spezifische physikalische und chemische Signale in der Flüssigkeit reagieren. Analog zur (Mikro-)Elektronik können diese aktiven Polymermaterialien durch verschiedene fotolithografische und mikrostrukturelle Methoden realisiert werden, um funktionelle Elemente mit hoher Skalierbarkeit zu erzeugen.\\ Die sogenannten chemofluidischen Schaltungen haben ein hohes funktionales Potenzial und ermöglichen eine 'wirkliche' on-chip Automatisierung, sind jedoch komplex im Systemdesign. In dieser Arbeit wird ein fortgeschrittenes Schaltungskonzept für eine planare mikrofluidische Chiparchitektur vorgestellt, das aus der frühen Ära der halbleiterbasierten Resistor-Transistor-Logik (RTL) hervorgeht. Beginnend mit dem Stand der Technik der mikrofluidischen Technologien, werden Materialien und Methoden dieser Arbeit näher beschrieben. Daraufhin wird die bevorzugte Herstellungstechnologie bewertet und verschiedene mikrofluidische Komponenten werden in Funktion und Design diskutiert. Die wichtigste Komponente, die es zu charakterisieren gilt, ist der auf Hydrogel basierende chemische Volumen-Phasenübergangstransistor (CVPT), der den Schlüssel zur Realisierung mikrofluidische Logikgatteroperationen darstellt. Dieses Schaltungskonzept (CVPT-RTL) ist robust und einfach im Design und kann mit gängigen Materialien und Fertigungstechniken realisiert werden. Zuletzt werden Anwendungsszenarien für das CVPT-RTL-Konzept vorgestellt und Empfehlungen für die fortlaufende Entwicklung angestellt.:1 The transistor: invention of the 20th century 2 Introduction to fluidic microsystems and the theoretical basics 2.1 Fluidic systems at the microscale 2.2 Overview of microfluidic chip fabrication 2.2.1 Common substrate materials for fluidic microsystems 2.2.2 Structuring polymer substrates for microfluidics 2.2.3 Polymer chip bonding technologies 2.3 Fundamentals and microfluidic transport processes 2.3.1 Fluid dynamics in miniaturized systems 2.3.2 Hagen-Poiseuille law: the fluidic resistance 2.3.3 Electronic and microfluidic circuit model analogy 2.3.4 Limits of the electro-fluidic analogy 2.4 Active components for microfluidic control 2.4.1 Fluid transport by integrated micropumps 2.4.2 Controlling fluids by on-chip microvalves 2.4.3 Hydrogel-based microvalve archetypes 2.5 LoC technologies: lost in translation? 2.6 Microfluidic platforms providing logic operations 2.6.1 Hybrids: MEMS-based logic concepts 2.6.2 Intrinsic logic operators for microfluidic circuits 2.7 Research objective: microfluidic hydrogel-based logic circuits 3 Stimuli-responsive polymers for microfluidics 3.1 Introduction to hydrogels 3.1.1 Application variety of hydrogels 3.1.2 Hydrogel microstructuring methods 3.2 Theory: stimuli-responsive hydrogels 3.3 PNIPAAm: a multi-responsive hydrogel 4 Design, production and characterization methods of hydrogel-based microfluidic systems 4.1 The semi-automated computer aided design approach for microfluidic systems 4.2 The applied design process 4.3 Fabrication of microfluidic chips 4.3.1 Photoresist master fabrication 4.3.2 Soft lithography for PDMS chip production 4.3.3 Assembling PDMS chips by plasma bonding 4.4 Integration of functional hydrogels in microfluidic chips 4.4.1 Preparation of a monomer solution for hydrogel synthesis 4.4.2 Integration methods 4.5 Effects on hydrogel photopolymerization and the role of integration method 4.5.1 Photopolymerization from monomer solutions: managing the diffusion of free radicals 4.5.2 Hydrogel adhesion and UV light intensity distribution in the polymerization chamber 4.5.3 Hydrogel shrinkage behavior of different adhesion types 4.6 Comparison of the integration methods 4.7 Characterization setups for hydrogel actuators and microfluidic measurements . 71 4.7.1 Optical characterization method to describe swelling behavior 4.7.2 Setup of a microfluidic test stand 4.8 Conclusion: design, production and characterization methods 5 VLSI technology for hydrogel-based microfluidics 5.1 Overview of photolithography methods 5.2 Standard UV photolithography system for microfluidic structures 5.3 Self-made UV lithography system suitable for the mVLSI 5.3.1 Lithography setup for the DFR and SU-8 master exposure 5.3.2 Comparison of mask-based UV induced crosslinking for DFR and SU-8 5.4 Mask-based UV photopolymerization for mVLSI hydrogel patterning 5.4.1 Lithography setup for the photopolymerization of hydrogels 5.4.2 Hydrogel photopolymerization: experiments and results 5.4.3 Troubleshooting: photopolymerization of hydrogels 5.5 Conclusion: mVLSI technologies for hydrogel-based LoCs 6 Components for chemofluidic circuit design 6.1 Passive components in microfluidics 6.1.1 Microfluidic resistor 6.1.2 Planar-passive microfluidic signal mixer 6.1.3 Phase separation: laminar flow signal splitter 6.1.4 Hydrogel-based microfluidic one-directional valves 6.2 Hydrogel-based active components 6.2.1 Reversible hydrogel-based valves 6.2.2 Hydrogel-based variable resistors 6.2.3 CVPT: the microfluidic transistor 6.3 Conclusion: components for chemofluidic circuits 7 Hydrogel-based logic circuits in planar microfluidics 7.1 Development of a planar CVPT logic concept 7.1.1 Challenges of planar microfluidics 7.1.2 Preparatory work and conceptional basis 7.2 The microfluidic CVPT-RTL concept 7.3 The CVPT-RTL NAND gate 7.3.1 Circuit optimization stabilizing the NAND operating mode 7.3.2 Role of laminar flow for the CVPT-RTL concept 7.3.3 Hydrogel-based components for improved switching reliability 7.4 One design fits all: the NOR, AND and OR gate 7.5 Control measures for cascaded systems 7.6 Application scenarios for the CVPT-RTL concept 7.6.1 Use case: automated cell growth system 7.6.2 Use case: chemofluidic converter 7.7 Conclusion: Hydrogel-based logic circuits 8 Summary and outlook 8.1 Scientific achievements 8.2 Summarized recommendations from this work Supplementary information SI.1 Swelling degree of BIS-pNIPAAm gels SI.2 Simulated ray tracing of UV lithography setup by WinLens® SI.3 Determination of the resolution using the intercept theorem SI.4 Microfluidic master mold test structures SI.4.1 Polymer and glass mask comparison SI.4.2 Resolution Siemens star in DFR SI.4.3 Resolution Siemens star in SU-8 SI.4.4 Integration test array 300 μm for DFR and SU-8 SI.4.5 Integration test array 100 μm for SU-8 SI.4.6 Microfluidic structure for different technology parameters SI.5 Microfluidic test setups SI.6 Supplementary information: microfluidic components SI.6.1 Compensation methods for flow stabilization in microfluidic chips SI.6.2 Planar-passive microfluidic signal mixer SI.6.3 Laminar flow signal splitter SI.6.4 Variable fluidic resistors: flow rate characteristics SI.6.5 CVPT flow rate characteristics for high Rout Standard operation procedure

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

Integrated Microwave Photonic Processors using Waveguide Mesh Cores

Integrated microwave photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint and cost. Application Specific Photonic Integrated Circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long-development times and costly implementations. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable Microwave Photonic processor, where a common hardware implemented by the combination of microwave, photonic and electronic subsystems, realizes different functionalities through programming. Here, we propose the first-ever generic-purpose Microwave Photonic processor concept and architecture. This versatile processor requires a powerful end-to-end field-based analytical model to optimally configure all their subsystems as well as to evaluate their performance in terms of the radiofrequency gain, noise and dynamic range. Therefore, we develop a generic model for integrated Microwave Photonics systems. The key element of the processor is the reconfigurable optical core. It requires high flexibility and versatility to enable reconfigurable interconnections between subsystems as well as the synthesis of photonic integrated circuits. For this element, we focus on a 2-dimensional photonic waveguide mesh based on the interconnection of tunable couplers. Within the framework of this Thesis, we have proposed two novel interconnection schemes, aiming for a mesh design with a high level of versatility. Focusing on the hexagonal waveguide mesh, we explore the synthesis of a high variety of photonic integrated circuits and particular Microwave Photonics applications that can potentially be performed on a single hardware. In addition, we report the first-ever demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate a world-record number of functionalities on a single photonic integrated circuit enabling over 30 different functionalities from the 100 that could be potentially obtained with a simple seven hexagonal cell structure. The resulting device can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks as well as quantum information systems. Our work is an important step towards this paradigm and sets the base for a new era of generic-purpose photonic integrated systems.Los dispositivos integrados de fotónica de microondas ofrecen soluciones optimizadas para los sistemas de información y comunicación. Generalmente, están compuestos por diferentes arquitecturas en las que subsistemas ópticos y electrónicos se integran para optimizar las prestaciones, el consumo, el tamaño y el coste del dispositivo final. Hasta ahora, los circuitos/chips de propósito específico se han diseñado para proporcionar una funcionalidad concreta, requiriendo así un número considerable de iteraciones entre las etapas de diseño, fabricación y medida, que origina tiempos de desarrollo largos y costes demasiado elevados. Una alternativa, inspirada por las FPGA (del inglés Field Programmable Gate Array), es el procesador fotónico programable. Este dispositivo combina la integración de subsistemas de microondas, ópticos y electrónicos para realizar, mediante la programación de los mismos y sus interconexiones, diferentes funcionalidades. En este trabajo, proponemos por primera vez el concepto del procesador de propósito general, así como su arquitectura. Además, con el fin de diseñar, optimizar y evaluar las prestaciones básicas del dispositivo, hemos desarrollado un modelo analítico extremo a extremo basado en las componentes del campo electromagnético. El modelo desarrollado proporciona como resultado la ganancia, el ruido y el rango dinámico global para distintas configuraciones de modulación y detección, en función de los subsistemas y su configuración. El elemento principal del procesador es su núcleo óptico reconfigurable. Éste requiere un alto grado de flexibilidad y versatilidad para reconfigurar las interconexiones entre los distintos subsistemas y para sintetizar los circuitos para el procesado óptico. Para este subsistema, proponemos el diseño de guías de onda reconfigurables para la creación de mallados bidimensionales. En el marco de esta tesis, hemos propuesto dos nuevos nodos de interconexión óptica para mallas reconfigurables, con el objetivo de obtener un mayor grado de versatilidad. Una vez escogida la malla hexagonal para el núcleo del procesador, hemos analizado la configuración de un gran número de circuitos fotónicos integrados y de funcionalidades de fotónica de microondas. El trabajo se ha completado con la demonstración de la primera malla reconfigurable integrada en un chip de silicio, demostrando además la síntesis de 30 de las 100 funcionalidades que potencialmente se pueden obtener con la malla diseñada compuesta de 7 celdas hexagonales. Este hecho supone un record frente a los sistemas de propósito específico. El sistema puede aplicarse en diferentes campos como las comunicaciones, los sensores químicos y biomédicos, el procesado de señales, la gestión y procesamiento de redes y los sistemas de información cuánticos. El conjunto del trabajo realizado representa un paso importante en la evolución de este paradigma, y sienta las bases para una nueva era de dispositivos fotónicos de propósito general.Els dispositius integrats de Fotònica de Microones oferixen solucions optimitzades per als sistemes d'informació i comunicació. Generalment, estan compostos per diferents arquitectures en què subsistemes òptics i electrònics s'integren per a optimitzar les prestacions, el consum, la grandària i el cost del dispositiu final. Fins ara, els circuits/xips de propòsit específic s'han dissenyat per a proporcionar una funcionalitat concreta, requerint així un nombre considerable d'iteracions entre les etapes de disseny, fabricació i mesura, que origina temps de desenrotllament llargs i costos massa elevats. Una alternativa, inspirada per les FPGA (de l'anglés Field Programmable Gate Array), és el processador fotònic programable. Este dispositiu combina la integració de subsistemes de microones, òptics i electrònics per a realitzar, per mitjà de la programació dels mateixos i les seues interconnexions, diferents funcionalitats. En este treball proposem per primera vegada el concepte del processador de propòsit general, així com la seua arquitectura. A més, a fi de dissenyar, optimitzar i avaluar les prestacions bàsiques del dispositiu, hem desenrotllat un model analític extrem a extrem basat en els components del camp electromagnètic. El model desenrotllat proporciona com resultat el guany, el soroll i el rang dinàmic global per a distintes configuracions de modulació i detecció, en funció dels subsistemes i la seua configuració. L'element principal del processador és el seu nucli òptic reconfigurable. Este requerix un alt grau de flexibilitat i versatilitat per a reconfigurar les interconnexions entre els distints subsistemes i per a sintetitzar els circuits per al processat òptic. Per a este subsistema, proposem el disseny de guies d'onda reconfigurables per a la creació de mallats bidimensionals. En el marc d'esta tesi, hem proposat dos nous nodes d'interconnexió òptica per a malles reconfigurables, amb l'objectiu d'obtindre un major grau de versatilitat. Una vegada triada la malla hexagonal per al nucli del processador, hem analitzat la configuració d'un gran nombre de circuits fotónicos integrats i de funcionalitats de fotónica de microones. El treball s'ha completat amb la demostració de la primera malla reconfigurable integrada en un xip de silici, demostrant a més la síntesi de 30 de les 100 funcionalitats que potencialment es poden obtindre amb la malla dissenyada composta de 7 cèl·lules hexagonals. Este fet suposa un rècord enfront dels sistemes de propòsit específic. El sistema pot aplicarse en diferents camps com les comunicacions, els sensors químics i biomèdics, el processat de senyals, la gestió i processament de xarxes i els sistemes d'informació quàntics. El conjunt del treball realitzat representa un pas important en l'evolució d'este paradigma, i assenta les bases per a una nova era de dispositius fotónicos de propòsit general.Pérez López, D. (2017). Integrated Microwave Photonic Processors using Waveguide Mesh Cores [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/91232TESI