Emerging applications of integrated optical microcombs for analogue RF and microwave photonic signal processing

We review new applications of integrated microcombs in RF and microwave photonic systems. We demonstrate a wide range of powerful functions including a photonic intensity high order and fractional differentiators, optical true time delays, advanced filters, RF channelizer and other functions, based on a Kerr optical comb generated by a compact integrated microring resonator, or microcomb. The microcomb is CMOS compatible and contains a large number of comb lines, which can serve as a high performance multiwavelength source for the transversal filter, thus greatly reduce the cost, size, and complexity of the system. The operation principle of these functions is theoretically analyzed, and experimental demonstrations are presented.Comment: 16 pages, 8 figures, 136 References. Photonics West 2018 invited paper, expanded version. arXiv admin note: substantial text overlap with arXiv:1710.00678, arXiv:1710.0861

Optimized fractional low and highpass filters of (1 + α) order on FPAA

This work proposes an optimum design and implementation of fractional-order Butterworth filter of order (1 + α), with the help of analog reconfigurable field-programmable analog array (FPAA). The designed filter coefficients are obtained after dual constraint optimization to balance the tradeoffs between magnitude error and stability margin together. The resulting filter ensures better robustness with less sensitivity to parameter variation and minimum least square error (LSE) in magnitude responses, passband and stopband errors as well as a better –3dB normalized frequency approximation at 1 rad/s and a stability margin. Finally, experimental results have shown both lowpass and highpass fractional step values. The FPAA-configured outputs represent the possibility to implement the real-time fractional filter behavior with close approximation to the theoretical design

High-Level Synthesis Based VLSI Architectures for Video Coding

High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard. Emerging applications like free-viewpoint video, 360degree video, augmented reality, 3D movies etc. require standardized extensions of HEVC. The standardized extensions of HEVC include HEVC Scalable Video Coding (SHVC), HEVC Multiview Video Coding (MV-HEVC), MV-HEVC+ Depth (3D-HEVC) and HEVC Screen Content Coding. 3D-HEVC is used for applications like view synthesis generation, free-viewpoint video. Coding and transmission of depth maps in 3D-HEVC is used for the virtual view synthesis by the algorithms like Depth Image Based Rendering (DIBR). As first step, we performed the profiling of the 3D-HEVC standard. Computational intensive parts of the standard are identified for the efficient hardware implementation. One of the computational intensive part of the 3D-HEVC, HEVC and H.264/AVC is the Interpolation Filtering used for Fractional Motion Estimation (FME). The hardware implementation of the interpolation filtering is carried out using High-Level Synthesis (HLS) tools. Xilinx Vivado Design Suite is used for the HLS implementation of the interpolation filters of HEVC and H.264/AVC. The complexity of the digital systems is greatly increased. High-Level Synthesis is the methodology which offers great benefits such as late architectural or functional changes without time consuming in rewriting of RTL-code, algorithms can be tested and evaluated early in the design cycle and development of accurate models against which the final hardware can be verified

On the design and implementation of a control system processor

In general digital control algorithms are multi-input multi-output (MIMO) recursive digital filters, but there are particular numerical requirements in control system processing for which standard processor devices are not well suited, in particular arising in systems with high sample rates. There is therefore a clear need to understand the numerical requirements properly, to identity optimised forms for implementing control laws, and to translate these into efficient processor architectures. By taking a considered view of the numerical and calculation requirements of control algorithms, it is possible to consider special purpose processors that provide well-targeted support of control laws. This thesis describes a compact, high-speed, special-purpose processor which offers a low-cost solution to implementing linear time invariant controllers. [Continues.

The design and implementation of a microprocessor controlled adaptive filter

This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement

Real-time FGPA implementation of a neuromorphic pitch detection system

This thesis explores the real-time implementation of a biologically inspired pitch detection system in digital electronics. Pitch detection is well understood and has been shown to occur in the initial stages of the auditory brainstem. By building such a system in digital hardware we can prove the feasibility of implementing neuromorphic systems using digital technology. This research not only aims to prove that such an implementation is possible but to investigate ways of achieving efficient and effective designs. We aim to achieve this complexity reduction while maintaining the fine granularity of the signal processing inherent in neural systems. By producing an efficient design we present the possibility of implementing the system within the available resources, thus producing a demonstrable system. This thesis presents a review of computational models of all the components within the pitch detection system. The review also identifies key issues relating to the efficient implementation and development of the pitch detection system. Four investigations are presented to address these issues for optimal neuromorphic designs of neuromorphic systems. The first investigation aims to produce the first-ever digital hardware implementation of the inner hair cell. The second investigation develops simplified models of the auditory nerve and the coincidence cell. The third investigation aims to reduce the most complex stage of the system, the stellate chopper cell array. Finally, we investigate implementing a large portion of the pitch detection system in hardware. The results contained in this thesis enable us to understand the feasibility of implementing such systems in real-time digital hardware. This knowledge may help researchers to make design decisions within the field of digital neuromorphic systems

Implementation of a coherent real-time noise radar system

The utilisation of continuous random waveforms for radar, that is, noise radar, has been extensively studied as a candidate for low probability of intercept operation. However, compared with the more traditional pulse-Doppler radar, noise radar systems are significantly more complicated to implement, which is likely why few systems exist. If noise radar systems are to see the light of day, system design, implementation, limitations etc., must be investigated. Therefore, the authors examine and detail the implementation of a real-time noise radar system on a field programmable gate array. The system is capable of operating with 100% duty cycle, 200\ua0MHz bandwidth, and 268\ua0ms integration time while processing a range of about 8.5\ua0km. Additionally, the system can perform real-time moving target compensation to reduce cell migration. System performance is primarily limited by the memory bandwidth of the off-chip dynamic random access memory