Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Direct charge measurement in Floating Gate transistors of Flash EEPROM using Scanning Electron Microscopy

We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retent ion measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique

Investigation of the scalability limitations of phase change random access memory

Ph.DDOCTOR OF PHILOSOPH

Resistive-RAM for Data Storage Applications.

Mainstream non-volatile memory technology, dominated by the floating gate transistor, has historically improved in density, performance and cost primarily by means of process scaling. This simple geometrical scaling now faces significant challenges due to constraints of electrostatics and reliability. Thus, novel non-transistor based memory paradigms are being widely explored. Among the various contenders for next generation storage technology, RRAM devices have got immense attention due to their high-speed, multilevel capability, scalability, simple structure, low voltage operation and high endurance. In this thesis, electrical and material characterization is carried out on a MIM device system and formation / annihilation of nanoscale filaments is shown to be the reason behind the resistance switching. The MIM system is optimized to include an in-cell resistor which is shown to improve device endurance and reduce stuck-at-one faults. For highest density, the devices were arranged in a crossbar geometry and vertically integrated on CMOS decoders to demonstrate the feasibility of practical data storage applications. Next, we show that these binary RRAM devices exhibit native stochastic nature of resistive switching. Even for a fixed voltage on the same device, the wait time associated with programming is not fixed and is random and broadly distributed. However, the probability of switching can be predicted and controlled by the programming pulse. These binary devices have been used to generate random bit-streams with predicable bias ratios in time and space domains. The ability to produce random bit-streams using binary resistive switching devices based on the native stochastic switching principle may potentially lead to novel non-von-Neumann computing paradigms. Further, sub-1nA operating current devices have been developed. This ultra-low current provides energy savings by minimizing programming, erase and read currents. Despite having such low currents, excellent retention, on/off ratio and endurance have been demonstrated. Finally a scalable approach to simple 3D stacking is discussed. By implementation of a vertical sidewall-based architecture, the number of critical lithography steps can be reduced. A vertical device structure based on a W / WOx / Pd material system is developed. This scalable architecture is well suited for development of analog memory and neuromorphic systems.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110461/1/sidgaba_1.pd

Optimization and Modelling of Semiconductor Devices in a 0.35 µm CMOS High Temperature Technology

Die vorliegende Arbeit beschäftigte sich mit der Optimierung und Modellierung von Bauelementen in einer 0,35 μm-CMOS-Technologie, die speziell für den Betrieb in einem erweiterten Temperaturbereich von −40 ℃ bis 250 ℃ vorgesehen ist. Bei dieser Technologie handelt es sich um eine Weiterentwicklung einer 1 μm-Technologie, die in weiten Teilen der Prozessierung modifiziert wurde. Durch die geringe Strukturbreite lassen sich komplexere Schaltungen und eine höhere Packungsdichte realisieren. Die Herstellung erfolgt in einer Dünnfilm-SOI-Technologie, die gegenüber einer üblicherweise verwendeten Bulk-Technologie deutliche Vorteile beim Hochtemperaturbetrieb bietet. Die zahlreichen Veränderungen in der neuen Technologie erforderten zunächst die Anpassung des elektrischen Verhaltens verschiedener Bauelemente an die gesetzten Spezifikationen. Dazu gehörte die Charakterisierung und die Parameterextraktion des verkleinerten Transistortyps. Die Optimierung des Durchbruchverhaltens einer Diode, die zum Schutz vor Überspannungspulsen eingesetzt wird, konnte durch die Anpassung der Dotierstoffkonzentrationen erreicht werden. Ebenfalls konnte eine Steigerung der Spannungsfestigkeit eines Hochspannungstransistors erzielt werden, indem u. a. der Avalanche-Effekt durch einen besseren Kanalanschluss vermieden wurde. Neben der Optimierung des elektrischen Verhaltens wurde auch das Zuverlässigkeitsverhalten der Bauelemente verbessert. Hierzu gehörte die Optimierung der Oxidqualität, welche durch Getterung von Kontaminationsatomen signifikant gesteigert werden konnte. Weiterhin konnte auch das Zuverlässigkeitsverhalten der Speicherzellen (EEPROM), welches durch die beiden Aspekte der Datenwechselstabilität und des Datenerhalts beschrieben wird, durch geometrische Veränderungen und Abschirmung der Zelle verbessert werden. Ein weiterer wichtiger Aspekt dieser Arbeit war die Entwicklung von Simulationsmodellen bestimmter Bauelemente in einem breiten Temperaturbereich. Zum einen konnte das elektrische Verhalten von Dioden bei Temperaturen zwischen −40 ℃ und 300 ℃ durch ein Makromodell genau nachgebildet werden. Zum anderen konnten die Datenwechselstabilität und der Datenerhalt der Speicherzelle bis zu einer Temperatur von 450 ℃ mithilfe eines Modells korrekt wiedergegeben werden. Die Modelle werden verwendet, um eine Vorhersage über das Verhalten von Bauelementen bei unterschiedlichen Temperaturen zu treffen, dienen als Hilfsmittel zur Optimierung der Bauelemente und sind für die Simulation von Schaltungen notwendig. Weiterhin wurden in der vorliegenden Arbeit neue Bauelemente vorgestellt, die vor allem für den Einsatz in einem breiten Temperaturbereich konzipiert sind. So wurde eine Schutzstruktur vor Überspannungspulsen vorgeschlagen, die bei einer Betriebsspannung von 3,3 V und einer Temperatur bis 250 ℃ eingesetzt werden soll. Dazu wurde entweder der Punch-Through- oder der Floating-Body-Effekt ausgenutzt, um das Bauelement ab einer bestimmten Spannung in den Leitungszustand zu versetzen. Für den Betrieb eines Hochspannungstransistors wurde in dieser Arbeit eine Bauweise vorgeschlagen, die es ermöglicht, die transistorspezifischen Eigenschaften, wie die Schwellenspannung oder den Leckstrom, in Abhängigkeit der Temperatur deutlich zu verbessern. Somit wurden in dieser Arbeit verschiedene kritische Bereiche einer CMOS-Technologie behandelt, die sich beim Hochtemperaturbetrieb ergeben. Dazu wurden Optimierungen im Bezug auf das elektrische Verhalten bzw. die Zuverlässigkeit vorgeschlagen und neue Bauelemente entwickelt, die vor allem für den Betrieb bei hohen Temperaturen ausgelegt sind. Zusätzlich wurden Simulationsmodelle für den erweiterten Temperaturbereich entwickelt, die nicht zuletzt zur Optimierung der Bauelemente beitragen.The present work focuses on the optimization and modeling of devices from a 0.35 μm technology developed for the operation in a wide temperature range from −40 ℃ up to 250 ℃. This technology is a further development of a 1 μm high temperature technology with various modifications in the processing flow. The shrink of the technology node allows to process more complex integrated circuits with a higher device density. For the wide temperature range, a thin film SOI technology is utilized that shows substantial benefits compared to the commonly used bulk technology. The numerous changes in the new technology require adjustment of the electric behavior of different devices to fulfill the specifications. Within the framework of this study one of the tasks was the characterization and the parameter extraction of the downsized transistor type. Further the breakdown behavior of a diode used for ESD protection was optimized by adapting the doping concentration. The breakdown voltage of a high voltage transistor was enhanced by a proper biasing of the channel area. Besides the optimization of the electric behavior the reliability of the devices was improved as well. For this purpose, the oxide quality was optimized by gettering contaminants. Furthermore the reliability of the memory cells (EEPROM) that can be described by the retention and endurance behavior was increased by geometrical optimization and a better isolation of the cell. In addition, simulation models were developed for specific devices to characterize the electric behavior in a wide temperature range. The characteristics of two different diodes at temperatures between −40 ℃ and 300 ℃ were simulated by a macro model. The endurance and retention behavior of a memory cell was also described by a macro model for temperatures up to 450 ℃. The models are used to predict the behavior of the devices at different temperatures, serve as auxiliary tools to optimize the devices and are also used for circuit simulations. Furthermore, new devices are developed in the present work to enable the operation in a wide temperature range. An ESD device is proposed to protect circuits with a low operating voltage of 3.3 V for temperatures up to 250 ℃. For this purpose, the punch through or floating body effect is used to bring the device in a conduction state at a certain trigger voltage. For the operation of high voltage transistor a new design is proposed, which allows to improve the transistor specific properties (for example leakage current or threshold voltage) at high temperatures. In summary, different critical parts of a CMOS technology designed for high temperature applications are investigated in this work. Optimizations with respect to the electric behavior and the reliability are proposed and new devices are developed to improve the performance at high temperatures. Additionally, simulation models are proposed to allow an accurate description of the electrical device behavior in a wide temperature range and which can also be used to optimize the device performance

Development and characterisation of a process technology for a 0.25µm SiGe:C RF-BiCMOS embedded flash memory

Integrating an embedded-flash memory module into a 0.25µm SiGe:C BiCMOS technology provides an important base for realising microelectronic systems that combine complex logic functionality with highest frequency analogue performance („System-on-Chip“). This dissertation presents for the first time an embedded flash memory module integrated in a 0.25µm SiGe:C BiCMOS process technology and describes the implementation into a process pilot line. The principle process flow and important process steps are described in detail, reviewing also the impact on the original BiCMOS process. The results are assessed geometrically by means of electron microscopy and electrically by characterisation of the developed electronic devices. The influence of important technological parameters is hereby investigated. The feasibility of the process for medium density memory production is finally demonstrated by a first 1-Mbit memory circuit that has been developed and produced based on the presented process technology

Cost effective technology applied to domotics and smart home energy management systems

Premio extraordinario de Trabajo Fin de Máster curso 2019/2020. Máster en Energías Renovables DistribuidasIn this document is presented the state of art for domotics cost effective technologies available on market nowadays, and how to apply them in Smart Home Energy Management Systems (SHEMS) allowing peaks shaving, renewable management and home appliance controls, always in cost effective context in order to be massively applied. Additionally, beyond of SHEMS context, it will be also analysed how to apply this technology in order to increase homes energy efficiency and monitoring of home appliances. Energy management is one of the milestones for distributed renewable energy spread; since renewable energy sources are not time-schedulable, are required control systems capable of the management for exchanging energy between conventional sources (power grid), renewable sources and energy storage sources. With the proposed approach, there is a first block dedicated to show an overview of Smart Home Energy Management Systems (SMHEMS) classical architecture and functional modules of SHEMS; next step is to analyse principles which has allowed some devices to become a cost-effective technology. Once the technology has been analysed, it will be reviewed some specific resources (hardware and software) available on marked for allowing low cost SHEMS. Knowing the “tools” available; it will be shown how to adapt classical SHEMS to cost effective technology. Such way, this document will show some specific applications of SHEMS. Firstly, in a general point of view, comparing the proposed low-cost technology with one of the main existing commercial proposals; and secondly, developing the solution for a specific real case.En este documento se aborda el estado actual de la domótica de bajo coste disponible en el mercado actualmente y cómo aplicarlo en los sistemas inteligentes de gestión energética en la vivienda (SHEMS) permitiendo el recorte de las puntas de demanda, gestión de energías renovables y control de electrodomésticos, siempre en el contexto del bajo coste, con el objetivo de lograr la máxima difusión de los SHEMS. Adicionalmente, más allá del contexto de la tecnología SHEMS, se analizará cómo aplicar esta tecnología para aumentar la eficiencia energética de los hogares y para la supervisión de los electrodomésticos. La gestión energética es uno de los factores principales para lograr la difusión de las energías renovables distribuidas; debido a que las fuentes de energía renovable no pueden ser planificadas, se requieren sistemas de control capaces de gestionar el intercambio de energía entre las fuentes convencionales (red eléctrica de distribución), energías renovables y dispositivos de almacenamiento energético. Bajo esta perspectiva, este documento presenta un primer bloque en el que se exponen las bases de la arquitectura y módulos funcionales de los sistemas inteligentes de gestión energética en la vivienda (SHEMS); el siguiente paso será analizar los principios que han permitido a ciertos dispositivos convertirse en dispositivos de bajo coste. Una vez analizada la tecnología, nos centraremos en los recursos (hardware y software) existentes que permitirán la realización de un SHEMS a bajo coste. Conocidas las “herramientas” a nuestra disposición, se mostrará como adaptar un esquema SHEMS clásico a la tecnología de bajo coste. Primeramente, comparando de modo genérico la tecnología de bajo coste con una de las principales propuestas comerciales de SHEMS, para seguidamente desarrollar la solución de bajo coste a un caso específico real

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms