Technology and reliability of normally-off GaN HEMTs with p-type gate

open4siopenMeneghini, Matteo*; Hilt, Oliver; Wuerfl, Joachim; Meneghesso, GaudenzioMeneghini, Matteo; Hilt, Oliver; Wuerfl, Joachim; Meneghesso, Gaudenzi

Mechanisms of Step-Stress Degradation In Carbon-Doped 0.15 μm AlGaN/GaN HEMTs for Power RF Applications

We discuss the degradation mechanisms of C-doped 0.15-μm gate AlGaN/GaN HEMTs tested by drain step-stress experiments. Experimental results show that these devices exhibit cumulative degradation effects during the step stress experiments in terms of either (i) transconductance (gm) decrease without any threshold-voltage (VT) change under OFF-state stress, or (ii) both VT and gm decrease under ON-state stress conditions. To aid the interpretation of the experiments, two-dimensional hydrodynamic device simulations were carried out. Based on obtained results, we attribute the gm decrease accumulating under OFF-state stress to hole emission from CN acceptor traps in the gate-drain access region of the buffer, resulting in an increase in the drain access resistance. On the other hand, under ON-state stress, channel hot electrons are suggested to be injected into the buffer under the gate and in the gate-drain region where they can be captured by CN traps, leading to VT and gm degradation, respectively

GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured