Packet Transactions: High-level Programming for Line-Rate Switches

Many algorithms for congestion control, scheduling, network measurement, active queue management, security, and load balancing require custom processing of packets as they traverse the data plane of a network switch. To run at line rate, these data-plane algorithms must be in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chipsets. The key challenge is that these algorithms create and modify algorithmic state. The key idea to achieve line-rate programmability for stateful algorithms is the notion of a packet transaction : a sequential code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient and natural way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated die-area overhead.Comment: 16 page

P4CEP: Towards In-Network Complex Event Processing

In-network computing using programmable networking hardware is a strong trend in networking that promises to reduce latency and consumption of server resources through offloading to network elements (programmable switches and smart NICs). In particular, the data plane programming language P4 together with powerful P4 networking hardware has spawned projects offloading services into the network, e.g., consensus services or caching services. In this paper, we present a novel case for in-network computing, namely, Complex Event Processing (CEP). CEP processes streams of basic events, e.g., stemming from networked sensors, into meaningful complex events. Traditionally, CEP processing has been performed on servers or overlay networks. However, we argue in this paper that CEP is a good candidate for in-network computing along the communication path avoiding detouring streams to distant servers to minimize communication latency while also exploiting processing capabilities of novel networking hardware. We show that it is feasible to express CEP operations in P4 and also present a tool to compile CEP operations, formulated in our P4CEP rule specification language, to P4 code. Moreover, we identify challenges and problems that we have encountered to show future research directions for implementing full-fledged in-network CEP systems.Comment: 6 pages. Author's versio

Relaxing state-access constraints in stateful programmable data planes

Supporting the programming of stateful packet forwarding functions in hardware has recently attracted the interest of the research community. When designing such switching chips, the challenge is to guarantee the ability to program functions that can read and modify data plane's state, while keeping line rate performance and state consistency. Current state-of-the-art designs are based on a very conservative all-or-nothing model: programmability is limited only to those functions that are guaranteed to sustain line rate, with any traffic workload. In effect, this limits the maximum time to execute state update operations. In this paper, we explore possible options to relax these constraints by using simulations on real traffic traces. We then propose a model in which functions can be executed in a larger but bounded time, while preventing data hazards with memory locking. We present results showing that such flexibility can be supported with little or no throughput degradation.Comment: 6 page

Teaching Memory Circuit Elements via Experiment-Based Learning

The class of memory circuit elements which comprises memristive, memcapacitive, and meminductive systems, is gaining considerable attention in a broad range of disciplines. This is due to the enormous flexibility these elements provide in solving diverse problems in analog/neuromorphic and digital/quantum computation; the possibility to use them in an integrated computing-memory paradigm, massively-parallel solution of different optimization problems, learning, neural networks, etc. The time is therefore ripe to introduce these elements to the next generation of physicists and engineers with appropriate teaching tools that can be easily implemented in undergraduate teaching laboratories. In this paper, we suggest the use of easy-to-build emulators to provide a hands-on experience for the students to learn the fundamental properties and realize several applications of these memelements. We provide explicit examples of problems that could be tackled with these emulators that range in difficulty from the demonstration of the basic properties of memristive, memcapacitive, and meminductive systems to logic/computation and cross-bar memory. The emulators can be built from off-the-shelf components, with a total cost of a few tens of dollars, thus providing a relatively inexpensive platform for the implementation of these exercises in the classroom. We anticipate that this experiment-based learning can be easily adopted and expanded by the instructors with many more case studies.Comment: IEEE Circuits and Systems Magazine (in press

A Complementary Resistive Switch-based Crossbar Array Adder

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic sneak currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.Comment: 12 pages, accepted for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), issue on Computing in Emerging Technologie

Neuromorphic, Digital and Quantum Computation with Memory Circuit Elements

Memory effects are ubiquitous in nature and the class of memory circuit elements - which includes memristors, memcapacitors and meminductors - shows great potential to understand and simulate the associated fundamental physical processes. Here, we show that such elements can also be used in electronic schemes mimicking biologically-inspired computer architectures, performing digital logic and arithmetic operations, and can expand the capabilities of certain quantum computation schemes. In particular, we will discuss few examples where the concept of memory elements is relevant to the realization of associative memory in neuronal circuits, spike-timing-dependent plasticity of synapses, digital and field-programmable quantum computing