Indirect Compensation Techniques for Three-Stage Fully-Differential Op-Amps

As CMOS technology continues to evolve, thesupply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fullydifferential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 μm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study

Multipath Miller Compensation for Switched-Capacitor Systems

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator

Design of operational amplifiers with feedforward multistage architecture in CMOS low voltage technology for biomedical instrumentation applications

Magnetic Resonance (MRI) is an imaging technique used to obtain anatomical and structural features of a patient’s body. The creation of a measurable signal is based on the varying water concentration throughout the body. The atoms which participate actively in such event are the hydrogen atoms from water, which create a varying magnetic field in response to a radiofrequency pulse. Such radiofrequency pulse is applied perpendicular to a main magnetic field created by a gradient coil, which is in charge of aligning the magnetic moments of hydrogen atoms. Upon application of the radiofrequency pulse, magnetic moments of hydrogen atoms rotate 90º with respect to the main field, creating a varying magnetic field which can be converted into a current through the use of coils. The detection of such current is achieved through the use of sensors, and constitutes a crucial step for the creation of an image based on the information emanating from the magnetic resonance equipment. Bearing in mind that a 1.5 Tesla MRI contains around 80 sensing components, the key element in MRI is the data acquisition block which forms part of each individual sensor. This data acquisition block contains a sensor, a band pass filter, and a band pass Analog to Digital Converter (ADC). From these three elements, the one in charge of the final resolution so that the digital part can appropriately process each sensor’s information is the ADC. Therefore, the accuracy of the ADC’s performance influences image processing steps to be performed afterwards for the final creation of an image. An Analog to Digital Converter can be built in several ways, either through a subsampling pipeline or band pass Sigma Delta. In both cases, the key elements which influence the resolution of the ADC are the operational amplifiers with which they are built up. Subsampling pipelines make use of operational amplifiers in order to sample the input signal in successive steps, whereas band pass Sigma Delta circuits use them to filter the quantification noise around a specified frequency. The ADC which will be used for the purpose of this work is a band pass Sigma Delta modulator whose bandwidth and center frequency are respectively 1MHz and 140MHz. The main objective of this work is to build a model of a real operational amplifier to be used in the filter of the ADC.Ingeniería Biomédic

Design of a Low Power 70MHz-110MHz Harmonic Rejection Filter with Class-AB Output Stage

An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2

A Four-stage Power and Area Efficient OTA with 30 × (400pf – 12nf) Capacitive Load Drive Range

Multistage operational transconductance amplifier (OTA) has been a major research focus as a solution to high DC Gain high Gain Bandwidth and wide voltage swing requirement on sub-micron devices. These system requirements, in addition to ultra-large capacitive load drivability (nF-range load capacitor), are useful in applications including LCD drivers, low dropout (LDO) linear regulators, headphone drivers, etc. The major drawback of multistage OTAs is the stability concerns since each added stage introduces low frequency poles. Numerous compensation schemes for three stage OTAs have been proposed in the past decade with only a few four stage OTA in literature. The proposed design is a four stage OTA which uses an active zero block (AZB) to provide left half plane (LHP) zero to help with phase degradation. AZB is embedded in the second stage ensuring reuse of existing block hence providing area and power savings. This design also uses single miller capacitor in the outer loop which ensures improved speed performance with minimal area overhead. A very reliable slew helper is implemented in this design to help with the large signal performance. The slew helper is only operational in the events slewing and does not affect the small signal performance. The proposed design achieves a DC gain of 114 dB, GBW > 1.77MHz and PM > 46.9⁰ for capacitive load ranging from 400pF–12nF (30x) which is the highest recorded range in literature for these type of compensation. It does this by consuming a total power of 143.5µW and an area of 0.007mm^2

High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error