Deep learning SIC approach for uplink MIMO-NOMA system

Abstract. Deep learning-based successive interference cancellation (DL-SIC) for uplink multiple-input multiple-output -non-orthogonal multiple access (MIMO-NOMA) system tries to optimize the users’ bit error rate (BER) and total mean square error (MSE) performance with higher order modulation schemes. The recent work of DL-SIC receiver design for users with a QPSK modulation scheme is investigated in this thesis to validate its performance as a potential alternative approach to traditional SIC receivers for NOMA users. Then, a DL-SIC receiver design for higher order modulation with less dependence on modulation order in the output layer is proposed, which enables us to decode the users with different modulation schemes. In our proposed design, we employ two deep neural networks (DNNs) for each SIC step. The system model is considered an M-antenna base station (BS) that serves two uplink users with a single antenna in the Rayleigh fading channel. The equivalent conventional minimum mean square error-based SIC (MMSE-SIC) and zero-forcing-based SIC (ZF-SIC) receivers are implemented as a baseline comparison. The simulation results showed that the BER performance of the proposed DL-SIC receiver for both users with QPSK modulation results in a 10 dB gain between BER of 10^(-2) and 10^(-3) compared to the ZF-SIC receiver. Furthermore, the performance difference between the proposed scheme and ZF-SIC is significantly high when both users transmit with 16QAM. Overall, the proposed DL-SIC receiver performs better in all signal-to-noise ratio (SNR) regions than the equivalent ZF-SIC receivers and also aids in mitigating the SIC error propagation problem. In addition, it improves the processing latency due to the benefits of the parallelized computing architecture and decreases the complexity of traditional SIC receivers

Performance of an Echo Canceller and Channel Estimator for On-Channel Repeaters in DVB-T/H Networks

This paper investigates the design and performance of an FIR echo canceller for on-channel repeaters in DVB-T/H network within the framework of the PLUTO project. The possible approaches for echo cancellation are briefly reviewed and the main guidelines for the design of such systems are presented. The main system parameters are discussed. The performance of an FIR echo canceller based on an open loop feedforward approach for channel estimation is tested for different radio channel conditions and for different number of taps of the FIR filter. It is shown that a minimum number of taps is recommended to achieve a certain mean rejection ratio or isolation depending on the type of channel. The expected degradation in performance due to the use of fixed point rather than floating point arithmetic in hardware implementation is presented for different number of bits. Channel estimation based on training sequences is investigated. The performance of Maximum Length Sequences and Constant Amplitude Zero Autocorrelation (CAZAC) Sequences is compared for different channels. Recommendations are given for training sequence type, length and level for DVB-T/H on-channel repeater deployment

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Analysis of Internally Bandlimited Multistage Cubic-Term Generators for RF Receivers

Adaptive feedforward error cancellation applied to correct distortion arising from third-order nonlinearities in RF receivers requires low-noise low-power reference cubic nonidealities. Multistage cubic-term generators utilizing cascaded nonlinear operations are ideal in this regard, but the frequency response of the interstage circuitry can introduce errors into the cubing operation. In this paper, an overview of the use of cubic-term generators in receivers relative to other applications is presented. An interstage frequency response plan is presented for a receiver cubic-term generator and is shown to function for arbitrary three-signal third-order intermodulation generation. The noise of such circuits is also considered and is shown to depend on the total incoming signal power across a particular frequency band. Finally, the effects of the interstage group delay are quantified in the context of a relevant communication standard requirement

Linearization techniques to suppress optical nonlinearity

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations

Minimum mean-squared error iterative successive parallel arbitrated decision feedback detectors for DS-CDMA systems

In this paper we propose minimum mean squared error (MMSE) iterative successive parallel arbitrated decision feedback (DF) receivers for direct sequence code division multiple access (DS-CDMA) systems. We describe the MMSE design criterion for DF multiuser detectors along with successive, parallel and iterative interference cancellation structures. A novel efficient DF structure that employs successive cancellation with parallel arbitrated branches and a near-optimal low complexity user ordering algorithm are presented. The proposed DF receiver structure and the ordering algorithm are then combined with iterative cascaded DF stages for mitigating the deleterious effects of error propagation for convolutionally encoded systems with both Viterbi and turbo decoding as well as for uncoded schemes. We mathematically study the relations between the MMSE achieved by the analyzed DF structures, including the novel scheme, with imperfect and perfect feedback. Simulation results for an uplink scenario assess the new iterative DF detectors against linear receivers and evaluate the effects of error propagation of the new cancellation methods against existing ones

Self-interference cancellation enabling high-throughput short-reach wireless full-duplex communication

In-band full-duplex (FD) wireless communication allows the simultaneous transmission and reception of data at the same frequency band, effectively doubling the spectral efficiency and data rate while reducing the latency. Previously published designs mostly target the self-interference (SI) cancellation in conventional wireless systems. In this paper, we focus on real-time SI cancellation for short-reach wireless FD systems. The superior signal quality of a point-to-point short-reach wireless system, allows the utilization of wideband communications to achieve a high throughput. Besides, in such wireless systems, the impacts of phase noise and nonlinear distortions are largely reduced, easing the SI cancellation. Moreover, the degradation of signal reception quality due to FD operation is experimentally evaluated in different environments. Experimental results of a prototype implementation show that a combination of antenna isolation and digital cancellation can already achieve an overall SI cancellation performance of 72.5 dB over a bandwidth of 123 MHz. This prototype can support a high-data-rate FD communication link of close to 1 Gbps up to 300 cm with an error vector magnitude lower than -26 dB in a typical indoor environment

Sparse Signal Processing Concepts for Efficient 5G System Design

As it becomes increasingly apparent that 4G will not be able to meet the emerging demands of future mobile communication systems, the question what could make up a 5G system, what are the crucial challenges and what are the key drivers is part of intensive, ongoing discussions. Partly due to the advent of compressive sensing, methods that can optimally exploit sparsity in signals have received tremendous attention in recent years. In this paper we will describe a variety of scenarios in which signal sparsity arises naturally in 5G wireless systems. Signal sparsity and the associated rich collection of tools and algorithms will thus be a viable source for innovation in 5G wireless system design. We will discribe applications of this sparse signal processing paradigm in MIMO random access, cloud radio access networks, compressive channel-source network coding, and embedded security. We will also emphasize important open problem that may arise in 5G system design, for which sparsity will potentially play a key role in their solution.Comment: 18 pages, 5 figures, accepted for publication in IEEE Acces