Synchronization Techniques for Burst-Mode Continuous Phase Modulation

Synchronization is a critical operation in digital communication systems, which establishes and maintains an operational link between transmitter and the receiver. As the advancement of digital modulation and coding schemes continues, the synchronization task becomes more and more challenging since the new standards require high-throughput functionality at low signal-to-noise ratios (SNRs). In this work, we address feedforward synchronization of continuous phase modulations (CPMs) using data-aided (DA) methods, which are best suited for burst-mode communications. In our transmission model, a known training sequence is appended to the beginning of each burst, which is then affected by additive white Gaussian noise (AWGN), and unknown frequency, phase, and timing offsets. Based on our transmission model, we derive the Cramer-Rao bound (CRB) for DA joint estimation of synchronization parameters. Using the CRB expressions, the optimum training sequence for CPM signals is proposed. It is shown that the proposed sequence minimizes the CRB for all three synchronization parameters asymptotically, and can be applied to the entire CPM family. We take advantage of the simple structure of the optimized training sequence in order to design a practical synchronization algorithm based on the maximum likelihood (ML) principles. The proposed DA algorithm jointly estimates frequency offset, carrier phase and symbol timing in a feedforward manner. The frequency offset estimate is first found by means of maximizing a one dimensional function. It is then followed by symbol timing and carrier phase estimation, which are carried out using simple closed-form expressions. We show that the proposed algorithm attains the theoretical CRBs for all synchronization parameters for moderate training sequence lengths and all SNR regions. Moreover, a frame synchronization algorithm is developed, which detects the training sequence boundaries in burst-mode CPM signals. The proposed training sequence and synchronization algorithm are extended to shaped-offset quadrature phase-shift keying (SOQPSK) modulation, which is considered for next generation aeronautical telemetry systems. Here, it is shown that the optimized training sequence outperforms the one that is defined in the draft telemetry standard as long as estimation error variances are considered. The overall bit error rate (BER) plots suggest that the optimized preamble with a shorter length can be utilized such that the performance loss is less than 0.5 dB of an ideal synchronization scenario

Carrier Recovery in burst-mode 16-QAM

Wireless communication systems such as multipoint communication systems (MCS) are becoming attractive as cost-effective means for providing network access in sparsely populated, rugged, or developing areas of the world. Since the radio spectrum is limited, it is desirable to use spectrally efficient modulation methods such as quadrature amplitude modulation (QAM) for high data rate channels. Many MCS employ time division multiple access (TDMA) and/or time division duplexing (TDD) techniques, in which transmissions operate in bursts. In many cases, a preamble of known symbols is appended to the beginning of each burst for carrier and symbol timing recovery (symbol timing is assumed known in this thesis). Preamble symbols consume bandwidth and power and are not used to convey information. In order for burst-mode communications to provide efficient data throughput, the synchronization time must be short compared to the user data portion of the burst. Traditional methods of communication system synchronization such as phase-locked loops (PLLs) have demonstrated reduced performance when operated in burst-mode systems. In this thesis, a feedforward (FF) digital carrier recovery technique to achieve rapid carrier synchronization is proposed. The estimation algorithms for determining carrier offsets in carrier acquisition and tracking in a linear channel environment corrupted by additive white Gaussian noise (AWGN) are described. The estimation algorithms are derived based on the theory of maximum likelihood (ML) parameter estimation. The estimations include data-aided (DA) carrier frequency and phase estimations in acquisition and non-data-aided (NDA) carrier phase estimation in tracking. The DA carrier frequency and phase estimation algorithms are based on oversampling of a known preamble. The NDA carrier phase estimation makes use of symbol timing knowledge and estimates are extracted from the random data portion of the burst. The algorithms have been simulated and tested using Matlab® to verify their functionalities. The performance of these estimators is also evaluated in the burst-mode operations for 16-QAM and compared in the presence of non-ideal conditions (frequency offset, phase offset, and AWGN). The simulation results show that the carrier recovery techniques presented in this thesis proved to be applicable to the modulation schemes of 16-QAM. The simulations demonstrate that the techniques provide a fast carrier acquisition using a short preamble (about 111 symbols) and are suitable for burst-mode communication systems

Robust Sampling Clock Recovery Algorithm for Wideband Networking Waveform of SDR

A novel technique for sampling clock recovery in a wideband networking waveform of a software defined radio is proposed. Sampling clock recovery is very important in wideband networking radio operation as it directly affects the Medium Access adaptive time slot switching rate. The proposed Sampling clock recovery algorithm consists of three stages. In the first stage, Sampling Clock Offset (SCO) is estimated at chip level. In the second stage, the SCO estimates are post-filtered to improve the tracking performance. We present a new post-filtering method namely Steady-State State-Space Recursive Least Squares with Adaptive Memory (S4RLSWAM). For the third stage of SCO compensation, a feedforward Lagrange interpolation based algorithm is proposed. Real-time hardware results have been presented to demonstrate the effectiveness of the proposed algorithms and architecture for systems requiring high data throughput. It is shown that both the proposed algorithms achieve better performance as compared to existing algorithms

Efficient Parallel Carrier Recovery for Ultrahigh Speed Coherent QAM Receivers with Application to Optical Channels

This work presents a new efficient parallel carrier recovery architecture suitable for ultrahigh speed intradyne coherent optical receivers (e.g., ≥100 Gb/s) with quadrature amplitude modulation (QAM). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only carrier frequency offset but also frequency fluctuations such as those induced by mechanical vibrations or power supply noise. Such carrier frequency fluctuations must be compensated since they lead to higher phase error variance in traditional feedforward CPR techniques, significantly degrading the receiver performance. In order to enable a parallel-processing implementation in multigigabit per second receivers, a new approximation to the DPLL computation is introduced. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while at the same time it provides a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed low latency parallel carrier recovery architecture.Fil: Gianni, Pablo. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Departamento de Electrónica. Laboratorio de Comunicaciones Digitales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Ferster, Laura. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Departamento de Electrónica. Laboratorio de Comunicaciones Digitales; ArgentinaFil: Corral Briones, Graciela. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Departamento de Electrónica. Laboratorio de Comunicaciones Digitales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Hueda, Mario Rafael. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Departamento de Electrónica. Laboratorio de Comunicaciones Digitales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentin

Synchronization for capacity -approaching coded communication systems

The dissertation concentrates on synchronization of capacity approaching error-correction codes that are deployed in noisy channels with very low signal-to-noise ratio (SNR). The major topics are symbol timing synchronization and frame synchronization.;Capacity-approaching error-correction codes, like turbo codes and low-density parity-check (LDPC) codes, are capable of reaching very low bit error rates and frame error rates in noisy channels by iterative decoding. To fully achieve the potential decoding capability of Turbo codes and LDPC codes, proper symbol timing synchronization, frame synchronization and channel state estimation are required. The dissertation proposes a joint estimator of symbol time delay and channel SNR for symbol timing recovery, and a maximum a posteriori (MAP) frame synchronizer for frame synchronization.;Symbol timing recovery is implemented by sampling and interpolation. The received signal is sampled multiple times per symbol period with unknown delay and unknown SNR. A joint estimator estimates the time delay and the SNR. The signal is rebuilt by interpolating available samples using estimated time delay. The intermediate decoding results enable decision-feedback estimation. The estimates of time delay and SNR are refined by iterative processing. This refinement improves the system performance significantly.;Usually the sampling rate is assumed to be a strict integer multiple of the symbol rate. However, in a practical system the local oscillators in the transmitter and the receiver may have random drifts. Therefore the sampling rate is no longer an exact multiple of the symbol rate, and the sampling time follows a random walk. This random walk may harm the system performance severely. The dissertation analyzes the effect of random time walks and proposes to mitigate the effect by overlapped sliding windows and iterative processing.;Frame synchronization is required to find the correct boundaries of codewords. MAP frame synchronization in the sense of minimizing the frame sync failure rate is investigated. The MAP frame synchronizer explores low-density parity-check attributes of the capacity-approaching codes. The accuracy of frame synchronization is adequate for considered coded systems to work reliably under very low SNR

Synchronization in all-digital QAM receivers

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection