768 research outputs found

    A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

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    A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

    Frequency Synthesizer Architectures for UWB MB-OFDM Alliance Application

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    Low power/low voltage techniques for analog CMOS circuits

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    Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

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    Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

    Tracking and Data Relay Satellite System (TDRSS) Range and Doppler Tracking System Observation Measurement and Modeling

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    This document gives detailed descriptions of the tracking services, signal generation and processing, range and Doppler extraction, and the principles and procedures involved in modeling range and Doppler observations via the Tracking and Data Relay Satellite System (TDRSS). Major topics discussed include the following: TDRSS telecommunication services, functional description of the TDRSS, tracking signal generation and processing, range and Doppler observations modeling, angular observed and computed measurement algorithms, and tracking data transmission format

    Design, implementation, evaluation and application of a 32-channel radio frequency signal generator for thermal magnetic resonance based anti-cancer treatment

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    Thermal Magnetic Resonance (ThermalMR) leverages radio frequency (RF)-induced heating to examine the role of temperature in biological systems and disease. To advance RF heating with multi-channel RF antenna arrays and overcome the shortcomings of current RF signal sources, this work reports on a 32-channel modular signal generator (SG(PLL)). The SG(PLL) was designed around phase-locked loop (PLL) chips and a field-programmable gate array chip. To examine the system properties, switching/settling times, accuracy of RF power level and phase shifting were characterized. Electric field manipulation was successfully demonstrated in deionized water. RF heating was conducted in a phantom setup using self-grounded bow-tie RF antennae driven by the SG(PLL). Commercial signal generators limited to a lower number of RF channels were used for comparison. RF heating was evaluated with numerical temperature simulations and experimentally validated with MR thermometry. Numerical temperature simulations and heating experiments controlled by the SG(PLL) revealed the same RF interference patterns. Upon RF heating similar temperature changes across the phantom were observed for the SG(PLL) and for the commercial devices. To conclude, this work presents the first 32-channel modular signal source for RF heating. The large number of coherent RF channels, wide frequency range and accurate phase shift provided by the SG(PLL) form a technological basis for ThermalMR controlled hyperthermia anti-cancer treatment

    Sub-0.1 degree phase locking of a single-photon interferometer

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    We report a single-photon Mach-Zehnder interferometer stabilized to a phase precision of 0.05 degrees over 15 hours. To lock the phase, we employ an auxiliary reference light at a different wavelength than the quantum signal. The developed phase locking operates continuously, with negligible crosstalk, and for an arbitrary phase of the quantum signal. Moreover, its performance is independent of intensity fluctuations of the reference. Since the presented method can be used in a vast majority of quantum interferometric networks it can significantly improve phase-sensitive applications in quantum communication and quantum metrology

    Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

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    Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory

    Low phase noise, high bandwidth frequency synthesis techniques

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 243-249).A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be <100kHz for adequate phase noise performance to be achieved. Using the proposed technique, quantization noise is reduced to the point where intrinsic noise sources (VCO, charge-pump, reference and PFD noise) ultimately limit noise performance. An analytical model that draws an analogy between fractional-N frequency synthesizers and MASH A digital-to-analog converters is proposed. Calculated performance of a synthesizer implementing the proposed quantization noise reduction techniques shows excellent agreement with simulation results of a behavioral model. Behavioral modeling techniques that progressively incorporate non-ideal circuit behavior based on SPICE level simulations are proposed. The critical circuits used to build the proposed synthesizer are presented.(cont.) These include a divider retiming circuit that avoids meta-stability related to synchronizing an asynchronous signal, a timing mismatch compensation block used by a dual divider path PFD, and a unit element current source design for reduced output phase noise. Measurement results of a prototype 0.18/m CMOS synthesizer show that quantization noise is suppressed by 29dB when the proposed synthesizer architecture is compared to 2nd order EA frequency synthesizer. The 1MHz closed loop bandwidth allows the synthesizer to be modulated by up to 1Mb/s GMSK data for use as a transmitter with 1.8GHz and 900MHz outputs. The analytical model is used to back extract on-chip mismatch parameters that are not directly measurable. This represents a new analysis technique that is useful in the characterization of fractional-N frequency synthesizers.by Scott Edward Meninger.Ph.D
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