Fault-tolerant computation using algebraic homomorphisms

Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.Includes bibliographical references (p. 193-196).Supported by the Defense Advanced Research Projects Agency, monitored by the U.S. Navy Office of Naval Research. N00014-89-J-1489 Supported by the Charles S. Draper Laboratories. DL-H-418472Paul E. Beckmann

Concurrent error detection in 2-D separable linear transform

As process technology continues to scale to smaller geometries and reduces the supply voltage, reliability of the resulting semiconductor becomes a greater concern. The effect of deep submicron noise, soft errors, variation, and aging degradation pose challenges on the functional correctness of VLSI systems and places roadblocks on reductions in scale. On the other side, as computing moves toward mobile, the energy efficiency of digital systems becomes one of the most important design metrics. However, reliability and energy efficiency are contradicting design requirements. Adding a voltage guard band is the most common method to mitigate the reliability impacts in such instances. Low power design technique like voltage over-scaling (VOS) even reduces the power by scaling the supply voltage just before data-dependant timing errors start to appear. Concurrent error detection is the solution to tackle reliability and energy-efficiency in a unified manner. Fault tolerance can be deployed at different design hierarchies. Given its low overhead, algorithm level error detection is an attractive approach. In this work, a generic weighted checksum code based error detection algorithm targeted generic 2-D separable linear transform is proposed. This technique encodes the input array at the 2-D linear trans- formation level, and algorithms are designed to operate on encoded data and produce encoded output data. The proposed error detection technique is a system-level method and therefore can be used in existing hardware or software 2-D linear transformation architectures with low overhead. The mathematic proof of the algorithm is provided within the scope of this dissertation. The checksum weighting vector for several common transforms are derived as examples, error detection cost and algorithm effectiveness are analyzed. In traditional fault tolerance study, the error is often evaluated at the boolean level. Many DSP applications, like 2-D linear transformation used in the multimedia compression system, do not require exactly correct results, but rather that the quality of the output is within the acceptable range. A generic quality aware error detection in the 2-D separable linear transform is proposed by extending the above property and defining the errors at the functional level. As an example, the quality-aware error detection technique is deployed on a low-power wavelet lifting transform architecture in JPEG2000. A low-cost Signal to Noise Ratio (SNR) aware detection logic based on proposed scheme is integrated into the discrete wavelet lifting transform architecture. This detection logic checks whether the image quality degradation caused by voltage over-scaling induced timing errors is acceptable and determines the optimal voltage set point in operating conditions at run time. This novel quality-based error detection approach is significantly different from traditional error detection schemes which look for exact data equivalence. A simulation result for one design shows that the supply voltage can be scaled down to 75% of the nominal voltage in typical process corner without significant image quality degradation, which translates to 9.15mW power consumption (44% power saving).Electrical and Computer Engineerin

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Low-cost duplication for separable error detection in computer arithmetic

Low-cost arithmetic error detection will be necessary in the future to ensure correct and safe system operation. However, current error detection mechanisms for arithmetic either have high area and energy overheads or are complex and offer incomplete protection against errors. Full duplication is simple, strong, and separable, but often is prohibitively costly. Alternative techniques such as arithmetic error coding require lower hardware and energy overheads than full duplication, but they do so at the expense of high design effort and error coverage holes. The goal of this research is to mitigate the deficiencies of duplication and arithmetic error coding to form an error detection scheme that may be readily employed in future systems. The techniques described by this work use a general duplication technique that employs an alternate number system in the duplicate arithmetic unit. These novel dual modular redundancy organizations are referred to as low-cost duplication, and they provide compelling efficiency and coverage advantages over prior arithmetic error detection mechanisms.Electrical and Computer Engineerin

A computer-aided design for digital filter implementation

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The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Small business innovation research program solicitation: Closing date July 16, 1990

This is the eighth annual solicitation by NASA addressed to small business firms, inviting them to submit proposals for research, or research and development, activities in some of the science and engineering areas of interest to NASA. The solicitation describes the Small Business Innovative Research (SBIR) program, identifies eligibility requirements, outlines the required proposal format and content, states proposal preparation and submission requirements, describes the proposal evaluation and award selection process, and provides other information to assist those interested in participating in NASA's SBIR program. It also identifies the technical topics and subtopics for which SBIR proposals are solicited. These cover a broad range of current NASA interests, but do not necessarily include all areas in which NASA plans or currently conducts research. High-risk high pay-off innovations are desired

Planning assistance for the NASA 30/20 GHz program. Network control architecture study.

Network Control Architecture for a 30/20 GHz flight experiment system operating in the Time Division Multiple Access (TDMA) was studied. Architecture development, identification of processing functions, and performance requirements for the Master Control Station (MCS), diversity trunking stations, and Customer Premises Service (CPS) stations are covered. Preliminary hardware and software processing requirements as well as budgetary cost estimates for the network control system are given. For the trunking system control, areas covered include on board SS-TDMA switch organization, frame structure, acquisition and synchronization, channel assignment, fade detection and adaptive power control, on board oscillator control, and terrestrial network timing. For the CPS control, they include on board processing and adaptive forward error correction control

An energy-efficient hardware system for robust and reliable heart rate monitoring

Cardiac arrhythmia, one of the most common causes of death in the world today, is not always effectively detected by regular examinations, as it usually occurs infrequently and suddenly. Therefore, real-time, continuous monitoring of the heart rate is needed to detect arrhythmia problems sooner and prevent their severe consequences. To make continuous monitoring possible and give it widespread acceptance, a portable heart rate monitoring system must have three key characteristics: (1) accuracy, (2) portability, and (3) long battery life. Previous studies have focused on addressing these problems separately, either improving the accuracy of the monitoring algorithm or the efficiency of the underlying hardware. This thesis proposes a robust and reliable heart rate monitoring system (RRHMS), in which both algorithm accuracy and hardware efficiency are considered. As a result, algorithmic optimizations are exploited to enable further hardware efficiency. In the RRHMS, robust heart rate monitoring is achieved by extracting heart rates from both electrocardiogram (ECG) and arterial blood pressure (ABP) signals and fusing them based on the signal qualities. Therefore, accurate heart rate data can be provided continuously, even when one signal is severely corrupted. Algorithmic optimizations are applied to merge the separate ECG and ABP processing steps into shared ones, which allows shared hardware modules and hence low-area (portable) hardware design. Also, an embedded hardware architecture framework is proposed for the design of the RRHMS hardware system. Coarse-grained functional units (FUs) can be easily added or removed in this framework, allowing for application-specific hardware optimization. Further, the application invariant properties are used to achieve low-overhead fault tolerance in the FUs to enhance reliability. Both ASIC and FPGA implementations of the RRHMS are able to accurately detect heart rates in real time while consuming only 1/2870 and 1/923 of the energy required by the Android implementation