242 research outputs found
Fault tolerance issues in nanoelectronics
The astonishing success story of microelectronics cannot go on indefinitely. In fact, once
devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected
to impair their behaviour. Fault tolerant techniques will then be required. The aim of this
thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient
error rates for a selection of nanoelectronic gates, based upon quantum cellular automata
and single electron devices, in which the electrostatic interaction between electrons is used
to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant
solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional
techniques are found to be unsuitable. A new technique, in which the voting approach of
triple modular redundancy (TMR) is extended by cascading TMR units composed of
nanogate clusters, is proposed and generalised to other voting approaches. For memory
chips, an error correcting code approach is found to be suitable. Various codes are
considered and a lookup table approach is proposed for encoding and decoding. We are
then able to give estimations for the redundancy level to be provided on nanochips, so as to
make their mean time between failures acceptable. It is found that, for logic chips, space
redundancies up to a few tens are required, if mean times between failures have to be of the
order of a few years. Space redundancy can also be traded for time redundancy. As for
memory chips, mean times between failures of the order of a few years are found to imply
both space and time redundancies of the order of ten
XOR multiplexing technique for nanocomputers
In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing technique. This hardware redundancy technique is based on a numerous duplication of faulty components. We analyze the error distributions of the XOR multiplexing unit and the error distributions of multiple stages of the XOR multiplexing system, then compare them to the NAND multiplexing unit and the NAND multiplexing multiple stages system, respectively. The simulation results show that XOR multiplexing is more reliable than NAND multiplexing. Bifurcation theory is used to analyze the fault-tolerant ability of the system and the results show that XOR multiplexing technique has a high fault-tolerant ability. Similarly to the NAND multiplexing technique, this fault-tolerant technique is a potentially effective fault tolerant technique for future nanoelectronics
Silicon CMOS architecture for a spin-based quantum computer
Recent advances in quantum error correction (QEC) codes for fault-tolerant
quantum computing \cite{Terhal2015} and physical realizations of high-fidelity
qubits in a broad range of platforms \cite{Kok2007, Brown2011, Barends2014,
Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the
construction of a quantum computer based on millions of interacting qubits.
However, the classical-quantum interface remains a nascent field of
exploration. Here, we propose an architecture for a silicon-based quantum
computer processor based entirely on complementary metal-oxide-semiconductor
(CMOS) technology, which is the basis for all modern processor chips. We show
how a transistor-based control circuit together with charge-storage electrodes
can be used to operate a dense and scalable two-dimensional qubit system. The
qubits are defined by the spin states of a single electron confined in a
quantum dot, coupled via exchange interactions, controlled using a microwave
cavity, and measured via gate-based dispersive readout \cite{Colless2013}. This
system, based entirely on available technology and existing components, is
compatible with general surface code quantum error correction
\cite{Terhal2015}, enabling large-scale universal quantum computation
Quantum-dot Cellular Automata: Review Paper
Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS. Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl
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