Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Embedded First-InFirst-Out (FIFO) memories are increasingly used in many IC designs.We have created a new full-custom embedded FIFO module withasynchronous read and write clocks, which is at least a factor twosmaller and also faster than SRAM-based and standard-cell-basedcounterparts. The detection qualities of the FIFO test for bothhard and weak resistive shorts and opens have been analyzed by anIFA-like method based on analog simulation. The defect coverage ofthe initial FIFO test for shorts in the bit-cell matrix has beenimproved by inclusion of an additional data background andlow-voltage testing; for low-resistant shorts, 100% defect coverageis obtained. The defect coverage for opens has been improved by anew test procedure which includes waitingperiods

Models for energy consumption of data structures and algorithms

EXCESS deliverable D2.1. More information at http://www.excess-project.eu/This deliverable reports our early energy models for data structures and algorithms based on both micro-benchmarks and concurrent algorithms. It reports the early results of Task 2.1 on investigating and modeling the trade-off between energy and performance in concurrent data structures and algorithms, which forms the basis for the whole work package 2 (WP2). The work has been conducted on the two main EXCESS platforms: (1) Intel platform with recent Intel multi-core CPUs and (2) Movidius embedded platform

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

A high speed fault-tolerant multimedia network and connectionless gateway for ATM networks.

by Patrick Lam Sze Fan.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 163-[170]).Chapter 1 --- Introduction --- p.1Chapter 2 --- Fault-tolerant CUM LAUDE NET --- p.7Chapter 2.1 --- Overview of CUM LAUDE NET --- p.7Chapter 2.2 --- Network architecture of CUM LAUDE NET --- p.8Chapter 2.3 --- Design of Router-node --- p.10Chapter 2.3.1 --- Architecture of the Router-node --- p.10Chapter 2.3.2 --- Buffers Arrangement of the Router-node --- p.12Chapter 2.3.3 --- Buffer transmission policies --- p.13Chapter 2.4 --- Protocols of CUM LAUDE NET --- p.14Chapter 2.5 --- Frame Format of CUM LAUDE NET --- p.15Chapter 2.6 --- Fault-tolerant (FT) and Auto-healing (AH) algorithms --- p.16Chapter 2.6.1 --- Overview of the algorithms --- p.16Chapter 2.6.2 --- Network Failure Scenarios --- p.18Chapter 2.6.3 --- Design and Implementation of the Fault Tolerant Algorithm --- p.19Chapter 2.6.4 --- Design and Implementation of the Auto Healing Algorithm --- p.26Chapter 2.6.5 --- Network Management Signals and Restoration Times --- p.27Chapter 2.6.6 --- Comparison of fault-tolerance features of other networks with the CUM LAUDE NET --- p.31Chapter 2.7 --- Chapter Summary --- p.31Chapter 3 --- Overview of the Asynchronous Transfer Mode (ATM) --- p.33Chapter 3.1 --- Introduction --- p.33Chapter 3.2 --- ATM Network Interfaces --- p.34Chapter 3.3 --- ATM Virtual Connections --- p.35Chapter 3.4 --- ATM Cell Format --- p.36Chapter 3.5 --- ATM Address Formats --- p.36Chapter 3.6 --- ATM Protocol Reference Model --- p.38Chapter 3.6.1 --- The ATM Layer --- p.39Chapter 3.6.2 --- The ATM Adaptation Layer --- p.39Chapter 3.7 --- ATM Signalling --- p.44Chapter 3.7.1 --- ATM Signalling Messages and Call Setup Procedures --- p.45Chapter 3.8 --- Interim Local Management Interface (ILMI) --- p.47Chapter 4 --- Issues of Connectionless Gateway --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- The Issues --- p.50Chapter 4.3 --- ATM Internetworking --- p.51Chapter 4.3.1 --- LAN Emulation --- p.52Chapter 4.3.2 --- IP over ATM --- p.53Chapter 4.3.3 --- Comparing IP over ATM and LAN Emulation --- p.59Chapter 4.4 --- Connection Management --- p.61Chapter 4.4.1 --- The Indirect Approach --- p.62Chapter 4.4.2 --- The Direct Approach --- p.63Chapter 4.4.3 --- Comparing the two approaches --- p.64Chapter 4.5 --- Protocol Conversion --- p.65Chapter 4.5.1 --- Selection of Protocol Converter --- p.68Chapter 4.6 --- Packet Forwarding Modes --- p.68Chapter 4.7 --- Bandwidth Assignment --- p.70Chapter 4.7.1 --- Bandwidth Reservation --- p.71Chapter 4.7.2 --- Fast Bandwidth Reservation --- p.72Chapter 4.7.3 --- Bandwidth Advertising --- p.72Chapter 4.7.4 --- Bandwidth Advertising with Cell Drop Detection --- p.73Chapter 4.7.5 --- Bandwidth Allocation on Source Demand --- p.73Chapter 4.7.6 --- The Common Problems --- p.74Chapter 5 --- Design and Implementation of the Connectionless Gateway --- p.77Chapter 5.1 --- Introduction --- p.77Chapter 5.1.1 --- Functions Definition of Connectionless Gateway --- p.79Chapter 5.2 --- Hardware Architecture of the Connectionless Gateway --- p.79Chapter 5.2.1 --- Imposed Limitations --- p.82Chapter 5.3 --- Software Architecture of the Connectionless Gateway --- p.83Chapter 5.3.1 --- TCP/IP Internals --- p.84Chapter 5.3.2 --- ATM on Linux --- p.85Chapter 5.4 --- Network Architecture --- p.88Chapter 5.4.1 --- IP Addresses Assignment --- p.90Chapter 5.5 --- Internal Structure of Connectionless Gateway --- p.90Chapter 5.5.1 --- Protocol Stacks of the Gateway --- p.90Chapter 5.5.2 --- Gateway Operation by Example --- p.93Chapter 5.5.3 --- Routing Table Maintenance --- p.97Chapter 5.6 --- Additional Features --- p.105Chapter 5.6.1 --- Priority Output Queues System --- p.105Chapter 5.6.2 --- Gateway Performance Monitor --- p.112Chapter 5.7 --- Setup an Operational ATM LAN --- p.117Chapter 5.7.1 --- SVC Connections --- p.117Chapter 5.7.2 --- PVC Connections --- p.119Chapter 5.8 --- Application of the Connectionless Gateway --- p.120Chapter 6 --- Performance Measurement of the Connectionless Gateway --- p.121Chapter 6.1 --- Introduction --- p.121Chapter 6.2 --- Experimental Setup --- p.121Chapter 6.3 --- Measurement Tools of the Experiments --- p.123Chapter 6.4 --- Descriptions of the Experiments --- p.124Chapter 6.4.1 --- Log Files --- p.125Chapter 6.5 --- UDP Control Rate Test --- p.126Chapter 6.5.1 --- Results and analysis of the UDP Control Rate Test --- p.127Chapter 6.6 --- UDP Maximum Rate Test --- p.138Chapter 6.6.1 --- Results and analysis of the UDP Maximum Rate Test --- p.138Chapter 6.7 --- TCP Maximum Rate Test --- p.140Chapter 6.7.1 --- Results and analysis of the TCP Maximum Rate Test --- p.140Chapter 6.8 --- Request/Response Test --- p.144Chapter 6.8.1 --- Results and analysis of the Request/Response Test --- p.144Chapter 6.9 --- Priority Queue System Verification Test --- p.149Chapter 6.9.1 --- Results and analysis of the Priority Queue System Verifi- cation Test --- p.150Chapter 6.10 --- Other Observations --- p.153Chapter 6.11 --- Solutions to Improve the Performance --- p.154Chapter 6.12 --- Future Development --- p.157Chapter 7 --- Conclusion --- p.158Bibliography --- p.163A List of Publications --- p.17