Memory Fault Simulator for Static-Linked Faults

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked fault

Airborne Advanced Reconfigurable Computer System (ARCS)

A digital computer subsystem fault-tolerant concept was defined, and the potential benefits and costs of such a subsystem were assessed when used as the central element of a new transport's flight control system. The derived advanced reconfigurable computer system (ARCS) is a triple-redundant computer subsystem that automatically reconfigures, under multiple fault conditions, from triplex to duplex to simplex operation, with redundancy recovery if the fault condition is transient. The study included criteria development covering factors at the aircraft's operation level that would influence the design of a fault-tolerant system for commercial airline use. A new reliability analysis tool was developed for evaluating redundant, fault-tolerant system availability and survivability; and a stringent digital system software design methodology was used to achieve design/implementation visibility

On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits

Fsm-Based Enhanced March C- Algorithm For Memory Built-In Self-Test

Algorithms plays an important role in the Memory Built-In Self-Test as its structure will define the fault coverage of the system. Thus, the improvement of the algorithms will allow more fault types being identified in single test. For MARCH C- algorithm, it was a quite balance algorithm as it has the ability to cover Address Decoder Fault, Stuck-At Fault, Transition Fault and Coupling Fault but it was not able to identify Read Destructive Fault and Data Retention Fault. To increase the fault coverage of the MARCH C- algorithm on that two fault types, some enhancements were needed to make on the algorithm. Through the analysis of the fault patterns and other algorithm, it was found that multiple read operation within a single MARCH element from MARCH-NU algorithm can aid in the identification of the Read Destructive Fault whereas having HOLD time in the MARCH 9N algorithm would expose the Data Retention Fault. By integrating both new fault identification methodologies into the MARCH C- algorithm and enhance it so that it would able to increase the identification of the Data Retention Fault and Read Destructive Fault by 100% and without causing any performance to interfere with the original fault identification ability. Besides that, the enhanced MARCH C- algorithm can structurally identify the fault types and differentiate among the behavioural faults (Data Retention Faults) and common memory faults as well as among Stuck-At Fault and Transition Fault. Fault injection test were carried out to ensure the coverage of the enhanced MARCH C- algorithm. It was having high passing rate which are 100% v identification of the Stuck-At Fault, Transition Fault, Data Retention Fault, Inversion Read Fault, Incorrect Read Fault and Read Destructive Fault. It also obtained 95.16% for the State Coupling Fault and Idempotent Coupling Fault. As a conclusion, the enhanced MARCH C- algorithm had increased its fault type identification in Data Retention Fault and Read Destructive Fault while having the ability to structurally identify the fault types

Automatic March tests generation for static and dynamic faults in SRAMs

New memory production modern technologies introduce new classes of faults usually referred to as dynamic memory faults. Although some hand-made March tests to deal with these new faults have been published, the problem of automatically generate March tests for dynamic faults has still to be addressed, in this paper we propose a new approach to automatically generate March tests with minimal length for both static and dynamic faults. The proposed approach resorts to a formal model to represent faulty behaviors in a memory and to simplify the generation of the corresponding tests

March Test Generation Revealed

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing static random access memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testin