Real-time complexity constrained encoding

Complex software appliances can be deployed on hardware with limited available computational resources. This computational boundary puts an additional constraint on software applications. This can be an issue for real-time applications with a fixed time constraint such as low delay video encoding. In the context of High Efficiency Video Coding (HEVC), a limited number of publications have focused on controlling the complexity of an HEVC video encoder. In this paper, a technique is proposed to control complexity by deciding between 2Nx2N merge mode and full encoding, at different Coding Unit (CU) depths. The technique is demonstrated in two encoders. The results demonstrate fast convergence to a given complexity threshold, and a limited loss in rate-distortion performance (on average 2.84% Bjontegaard delta rate for 40% complexity reduction)

A Motion Estimation based Algorithm for Encoding Time Reduction in HEVC

High Efficiency Video Coding (HEVC) is a video compression standard that offers 50% more efficiency at the expense of high encoding time contrasted with the H.264 Advanced Video Coding (AVC) standard. The encoding time must be reduced to satisfy the needs of real-time applications. This paper has proposed the Multi- Level Resolution Vertical Subsampling (MLRVS) algorithm to reduce the encoding time. The vertical subsampling minimizes the number of Sum of Absolute Difference (SAD) computations during the motion estimation process. The complexity reduction algorithm is also used for fast coding the coefficients of the quantised block using a flag decision. Two distinct search patterns are suggested: New Cross Diamond Diamond (NCDD) and New Cross Diamond Hexagonal (NCDH) search patterns, which reduce the time needed to locate the motion vectors. In this paper, the MLRVS algorithm with NCDD and MLRVS algorithm with NCDH search patterns are simulated separately and analyzed. The results show that the encoding time of the encoder is decreased by 55% with MLRVS algorithm using NCDD search pattern and 56% with MLRVS using NCDH search pattern compared to HM16.5 with Test Zone (TZ) search algorithm. These results are achieved with a slight increase in bit rate and negligible deterioration in output video quality

Fast Motion Estimation’s Configuration Using Diamond Pattern and ECU, CFM, and ESD Modes for Reducing HEVC Computational Complexity

The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation

Efficient HEVC-based video adaptation using transcoding

In a video transmission system, it is important to take into account the great diversity of the network/end-user constraints. On the one hand, video content is typically streamed over a network that is characterized by different bandwidth capacities. In many cases, the bandwidth is insufficient to transfer the video at its original quality. On the other hand, a single video is often played by multiple devices like PCs, laptops, and cell phones. Obviously, a single video would not satisfy their different constraints. These diversities of the network and devices capacity lead to the need for video adaptation techniques, e.g., a reduction of the bit rate or spatial resolution. Video transcoding, which modifies a property of the video without the change of the coding format, has been well-known as an efficient adaptation solution. However, this approach comes along with a high computational complexity, resulting in huge energy consumption in the network and possibly network latency. This presentation provides several optimization strategies for the transcoding process of HEVC (the latest High Efficiency Video Coding standard) video streams. First, the computational complexity of a bit rate transcoder (transrater) is reduced. We proposed several techniques to speed-up the encoder of a transrater, notably a machine-learning-based approach and a novel coding-mode evaluation strategy have been proposed. Moreover, the motion estimation process of the encoder has been optimized with the use of decision theory and the proposed fast search patterns. Second, the issues and challenges of a spatial transcoder have been solved by using machine-learning algorithms. Thanks to their great performance, the proposed techniques are expected to significantly help HEVC gain popularity in a wide range of modern multimedia applications

Algorithms and methods for video transcoding.

Video transcoding is the process of dynamic video adaptation. Dynamic video adaptation can be defined as the process of converting video from one format to another, changing the bit rate, frame rate or resolution of the encoded video, which is mainly necessitated by the end user requirements. H.264 has been the predominantly used video compression standard for the last 15 years. HEVC (High Efficiency Video Coding) is the latest video compression standard finalised in 2013, which is an improvement over H.264 video compression standard. HEVC performs significantly better than H.264 in terms of the Rate-Distortion performance. As H.264 has been widely used in the last decade, a large amount of video content exists in H.264 format. There is a need to convert H.264 video content to HEVC format to achieve better Rate-Distortion performance and to support legacy video formats on newer devices. However, the computational complexity of HEVC encoder is 2-10 times higher than that of H.264 encoder. This makes it necessary to develop low complexity video transcoding algorithms to transcode from H.264 to HEVC format. This research work proposes low complexity algorithms for H.264 to HEVC video transcoding. The proposed algorithms reduce the computational complexity of H.264 to HEVC video transcoding significantly, with negligible loss in Rate-Distortion performance. This work proposes three different video transcoding algorithms. The MV-based mode merge algorithm uses the block mode and MV variances to estimate the split/non-split decision as part of the HEVC block prediction process. The conditional probability-based mode mapping algorithm models HEVC blocks of sizes 16×16 and lower as a function of H.264 block modes, H.264 and HEVC Quantisation Parameters (QP). The motion-compensated MB residual-based mode mapping algorithm makes the split/non-split decision based on content-adaptive classification models. With a combination of the proposed set of algorithms, the computational complexity of the HEVC encoder is reduced by around 60%, with negligible loss in Rate-Distortion performance, outperforming existing state-of-art algorithms by 20-25% in terms of computational complexity. The proposed algorithms can be used in computation-constrained video transcoding applications, to support video format conversion in smart devices, migration of large-scale H.264 video content from host servers to HEVC, cloud computing-based transcoding applications, and also to support high quality videos over bandwidth-constrained networks

Hardware based High Accuracy Integer Motion Estimation and Merge Mode Estimation

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 이혁재.HEVC는 H.264/AVC 대비 2배의 뛰어난 압축 효율을 가지지만, 많은 압축 기술이 사용됨으로써, 인코더 측의 계산 복잡도를 크게 증가시켰다. HEVC의 높은 계산 복잡도를 줄이기 위한 많은 연구들이 이루어졌지만, 대부분의 연구들은 H.264/AVC를 위한 계산 복잡도 감소 방법을 확장 적용하는 데에 그쳐, 만족스럽지 않은 계산 복잡도 감소 성능을 보이거나, 지나치게 큰 압축 효율 손실을 동반하여 HEVC의 최대 압축 성능을 끌어내지 못했다. 특히 앞서 연구된 하드웨어 기반의 인코더는 실시간 인코더의 실현이 우선되어 압축 효율의 희생이 매우 크다. 그러므로, 본 연구에서는 하드웨어 기반 Inter prediction의 고속화를 이룸과 동시에 HEVC가 가진 압축 성능의 손실을 최소화하고, 실시간 코딩이 가능한 하드웨어 구조를 제안하였다. 본 연구에서 제안한 bottom-up MV 예측 방법은 기존의 공간적, 시간적으로 인접한 PU로부터 MV를 예측하는 방법이 아닌, HEVC의 계층적으로 인접한 PU로부터 MV를 예측하는 방법을 제안하여 MV 예측의 정확도를 큰 폭으로 향상시켰다. 결과적으로 압축 효율의 변화 없이 IME의 계산 복잡도를 67% 감소시킬 수 있었다. 또한, 본 연구에서는 제안된 bottom-up IME 알고리즘을 적용하여 실시간 동작이 가능한 하드웨어 기반의 IME를 제안하였다. 기존의 하드웨어 기반 IME는 고속 IME 알고리즘이 갖는 단계별 의존성으로 인한 idle cycle의 발생과 참조 데이터 접근 문제로 인해, 고속 IME 알고리즘을 사용하지 않거나 또는 하드웨어에 맞게 고속 IME 알고리즘을 수정하였기 때문에 압축 효율의 저하가 수 퍼센트 이상으로 매우 컸다. 그러나 본 연구에서는 고속 IME 알고리즘인 TZS 알고리즘을 채택하여 TZS 알고리즘의 계산 복잡도 감소 성능을 훼손하지 않는 하드웨어 기반의 IME를 제안하였다. 고속 IME 알고리즘을 하드웨어에서 사용하기 위해서 다음 세 가지 사항을 제안하고 하드웨어에 적용하였다. 첫 째로, 고속 IME 알고리즘의 고질적 문제인 idle cycle 발생 문제를 서로 다른 참조 픽쳐와 서로 다른 depth에 대한 IME를 컨텍스트 스위칭을 통해 해결하였다. 둘 째로, 참조 데이터로의 빠르고 자유로운 접근을 위해 참조 데이터의 locality 이용한 multi bank SRAM 구조를 제안하였다. 셋 째로, 지나치게 자유로운 참조 데이터 접근이 발생시키는 대량의 스위칭 mux의 사용을 피하기 위해 탐색 중심을 기준으로 하는 제한된 자유도의 참조 데이터 접근을 제안하였다. 결과 제안된 IME 하드웨어는 HEVC의 모든 블록 크기를 지원하면서, 참조 픽처 4장를 사용하여, 4k UHD 영상을 60fps의 속도로 처리할 수 있으며 이 때 압축 효율의 손실은 0.11%로 거의 나타나지 않는다. 이 때 사용되는 하드웨어 리소스는 1.27M gates이다. HEVC에 새로이 채택된 merge mode estimation은 압축 효율 개선 효과가 뛰어난 새로운 기술이지만, 매 PU 마다 계산 복잡도의 변동 폭이 커서 하드웨어로 구현되는 경우 하드웨어 리소스의 낭비가 많다. 그러므로 본 연구에서는 효율적인 하드웨어 기반 MME 방법과 하드웨어 구조를 함께 제안하였다. 기존 MME 방식은 이웃 PU에 의해 보간 필터 적용 여부가 결정되기 때문에, 보간 필터의 사용률은 50% 이하를 나타낸다. 그럼에도 불구하고 하드웨어는 보간 필터를 사용하는 경우에 맞추어 설계되어왔기 때문에 하드웨어 리소스의 사용 효율이 낮았다. 본 연구에서는 가장 하드웨어 리소스를 많이 사용하는 세로 방향 보간 필터를 절반 크기로 줄인 두 개의 데이터 패스를 갖는 MME 하드웨어 구조를 제안하였고, 높은 하드웨어 사용률을 유지하면서 압축 효율 손실을 최소화 하는 merge 후보 할당 알고리즘을 제안하였다. 결과, 기존 하드웨어 기반 MME 보다 24% 적은 하드웨어 리소스를 사용하면서도 7.4% 더 빠른 수행 시간을 갖는 새로운 하드웨어 기반의 MME를 달성하였다. 제안된 하드웨어 기반의 MME는 460.8K gates의 하드웨어 리소스를 사용하고 4k UHD 영상을 30 fps의 속도로 처리할 수 있다.제 1 장 서 론 1 1.1 연구 배경 1 1.2 연구 내용 3 1.3 공통 실험 환경 5 1.4 논문 구성 6 제 2 장 관련 연구 7 2.1 HEVC 표준 7 2.1.1 쿼드-트리 기반의 계층적 블록 구조 7 2.1.2 HEVC 의 Inter Prediction 9 2.2 화면 간 예측의 속도 향상을 위한 이전 연구 17 2.2.1 고속 Integer Motion Estimation 알고리즘 17 2.2.2 고속 Merge Mode Estimation 알고리즘 20 2.3 화면 간 예측 하드웨어 구조에 대한 이전 연구 21 2.3.1 하드웨어 기반 Integer Motion Estimation 연구 21 2.3.2 하드웨어 기반 Merge Mode Estimation 연구 25 제 3 장 Bottom-up Integer Motion Estimation 26 3.1 서로 다른 계층 간의 Motion Vector 관계 관찰 26 3.1.1 서로 다른 계층 간의 Motion Vector 관계 분석 26 3.1.2 Top-down 및 Bottom-up 방향의 Motion Vector 관계 분석 30 3.2 Bottom-up Motion Vector Prediction 33 3.3 Bottom-up Integer Motion Estimation 37 3.3.1 Bottom-up Integer Motion Estimation - Single MVP 37 3.3.2 Bottom-up Integer Motion Estimation - Multiple MVP 38 3.4 실험 결과 40 제 4 장 하드웨어 기반 Integer Motion Estimation 46 4.1 Bottom-up Integer Motion Estimation의 하드웨어 적용 46 4.2 하드웨어를 위한 수정된 Test Zone Search 47 4.2.1 SAD-tree를 활용한 CU 내 PU의 병렬 처리 47 4.2.2 Grid 기반의 Sampled Raster Search 53 4.2.3 서로 다른 PU 간의 중복 연산 제거 55 4.3 Idle cycle이 감소된 5-stage 파이프라인 스케줄 56 4.3.1 파이프라인 스테이지 별 동작 56 4.3.2 Test Zone Search의 의존성으로 인한 Idle cycle 도입 58 4.3.3 컨텍스트 스위칭을 통한 Idle cycle 감소 60 4.4 고속 동작을 위한 참조 데이터 공급 방법 63 4.4.1 참조 데이터 접근 패턴 및 접근 지연 발생 시 문제점 63 4.4.2 Search Points의 Locality를 활용한 참조 데이터 접근 64 4.4.3 단일 cycle 참조 데이터 접근을 위한 Multi Bank 메모리 구조 66 4.4.4 참조 데이터 접근의 자유도 제어를 통한 스위칭 복잡도 저감 방법 68 4.5 하드웨어 구조 72 4.5.1 전체 하드웨어 구조 72 4.5.2 하드웨어 세부 스케줄 78 4.6 하드웨어 구현 결과 및 실험 결과 82 4.6.1 하드웨어 구현 결과 82 4.6.2 수행 시간 및 압축 효율 84 4.6.3 제안 방법 적용 단계 별 성능 변화 88 4.6.4 이전 연구와의 비교 91 제 5 장 하드웨어 기반 Merge Mode Estimation 96 5.1 기존 Merge Mode Estimation의 하드웨어 관점에서의 고찰 96 5.1.1 기존 Merge Mode Estimation 96 5.1.2 기존 Merge Mode Estimation 하드웨어 구조 및 분석 98 5.1.3 기존 Merge Mode Estimation의 하드웨어 사용률 저하 문제 100 5.2 연산량 변동폭을 감소시킨 새로운 Merge Mode Estimation 103 5.3 새로운 Merge Mode Estimation의 하드웨어 구현 106 5.3.1 후보 타입 별 독립적 path를 갖는 하드웨어 구조 106 5.3.2 하드웨어 사용률을 높이기 위한 적응적 후보 할당 방법 109 5.3.3 적응적 후보 할당 방법을 적용한 하드웨어 스케줄 111 5.4 실험 결과 및 하드웨어 구현 결과 114 5.4.1 수행 시간 및 압축 효율 변화 114 5.4.2 하드웨어 구현 결과 116 제 6 장 Overall Inter Prediction 117 6.1 CTU 단위의 3-stage 파이프라인 Inter Prediction 117 6.2 Two-way Encoding Order 119 6.2.1 Top-down 인코딩 순서와 Bottom-up 인코딩 순서 119 6.2.2 기존 고속 알고리즘과 호환되는 Two-way Encoding Order 120 6.2.3 기존 고속 알고리즘과 결합 및 비교 실험 결과 123 제 7 장 Next Generation Video Coding으로의 확장 127 7.1 Bottom-up Motion Vector Prediction의 확장 127 7.2 Bottom-up Integer Motion Estimation의 확장 130 제 8 장 결 론 132Docto

VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard

This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. For 11 different configurations, hardware cost as well as the coding efficiency are quantified and are compared through a graphical analysis to make design decisions. It has been shown that using smaller block sizes (e.g. 4 × 4) imposes significantly larger hardware requirements at the expense of modest improvements in coding efficiency. Secondly, based on the analysis on various configurations, one configuration is chosen and algorithm improvements are presented to further reduce hardware implementation cost of the selected configuration. Overall, the proposed changes provide 56 × on-chip bandwidth, 151 × off-chip bandwidth, 4.3 × core area and 4.5 × on-chip memory area savings when compared to the hardware implementation of the HM-3.0 design.Texas Instruments Incorporate

Compression vidéo basée sur l'exploitation d'un décodeur intelligent

This Ph.D. thesis studies the novel concept of Smart Decoder (SDec) where the decoder is given the ability to simulate the encoder and is able to conduct the R-D competition similarly as in the encoder. The proposed technique aims to reduce the signaling of competing coding modes and parameters. The general SDec coding scheme and several practical applications are proposed, followed by a long-term approach exploiting machine learning concept in video coding. The SDec coding scheme exploits a complex decoder able to reproduce the choice of the encoder based on causal references, eliminating thus the need to signal coding modes and associated parameters. Several practical applications of the general outline of the SDec scheme are tested, using different coding modes during the competition on the reference blocs. Despite the choice for the SDec reference block being still simple and limited, interesting gains are observed. The long-term research presents an innovative method that further makes use of the processing capacity of the decoder. Machine learning techniques are exploited in video coding with the purpose of reducing the signaling overhead. Practical applications are given, using a classifier based on support vector machine to predict coding modes of a block. The block classification uses causal descriptors which consist of different types of histograms. Significant bit rate savings are obtained, which confirms the potential of the approach.Cette thèse de doctorat étudie le nouveau concept de décodeur intelligent (SDec) dans lequel le décodeur est doté de la possibilité de simuler l’encodeur et est capable de mener la compétition R-D de la même manière qu’au niveau de l’encodeur. Cette technique vise à réduire la signalisation des modes et des paramètres de codage en compétition. Le schéma général de codage SDec ainsi que plusieurs applications pratiques sont proposées, suivis d’une approche en amont qui exploite l’apprentissage automatique pour le codage vidéo. Le schéma de codage SDec exploite un décodeur complexe capable de reproduire le choix de l’encodeur calculé sur des blocs de référence causaux, éliminant ainsi la nécessité de signaler les modes de codage et les paramètres associés. Plusieurs applications pratiques du schéma SDec sont testées, en utilisant différents modes de codage lors de la compétition sur les blocs de référence. Malgré un choix encore simple et limité des blocs de référence, les gains intéressants sont observés. La recherche en amont présente une méthode innovante qui permet d’exploiter davantage la capacité de traitement d’un décodeur. Les techniques d’apprentissage automatique sont exploitées pour but de réduire la signalisation. Les applications pratiques sont données, utilisant un classificateur basé sur les machines à vecteurs de support pour prédire les modes de codage d’un bloc. La classification des blocs utilise des descripteurs causaux qui sont formés à partir de différents types d’histogrammes. Des gains significatifs en débit sont obtenus, confirmant ainsi le potentiel de l’approche

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware

Heterogeneous systems on a single chip composed of CPU, Graphical Processing Unit (GPU), and Field Programmable Gate Array (FPGA) are expected to emerge in near future. In this context, the System on Chip (SoC) can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation is one such task that can be accelerated using FPGA and GPU for high performance H.264/AVC encoder implementation. In most of works on parallel implementation of motion estimation, the bit rate cost of motion vectors is generally ignored. On the contrary, this paper presents a fast rate-distortion optimized parallel motion estimation algorithm implemented on GPU using OpenCL and FPGA/ASIC using VHDL. The predicted motion vectors are estimated from temporally preceding motion vectors and used for evaluating the bit rate cost of the motion vectors simultaneously. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable ratedistortion performance with respect to sequential fast motion estimation algorithm