Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Pipeline ADC with a Nonlinear Gain Stage and Digital Correction

The goal of this work was to design a pipeline analog to digital converter that can be calibrated and corrected in the digital domain. The scope of this work included the design, simulation and layout of major analog design blocks. The design uses an open loop gain stage to reduce power consumption, increase speed and relax small process size design requirements. These nonlinearities are corrected using a digital correction algorithm implemented in MATLAB

The design of calibration circuit for analog-to-digital converter (ADC).

Dua jenis (Jenis 1 dan Jenis 2) litar tentukuran untuk ADC saluran maklumat telah direka bentuk menggunakan kod Verilog-A yang boleh didapati daripada arkib ahdlib dari alat simulasi perisian Cadence Virtuoso. Kod yang diguna pakai telah diubahsuai bagi memenuhi litar tentukuran yang dicadangkan. Dua blok ADC saluran maklumat yang sama (ADC saluran maklumat 1 dan ADC saluran maklumat 2) direalisasi menggunakan 130nm proses Silterra CMOS dengan setiap ADC mempunyai output digital 4-bit masing-masing. Voltan rujukan pada 600mV digunakan dalam operasi ADC saluran maklumat ini dengan bekalan kuasa 1.2V bagi Vdd dan 0V bagi Vss. ADC saluran maklumat beroperasi pada frekuensi pensampelan 2.2727MHz dengan frekuensi input dari DC ke 1.1364 MHz. Julat Voltan input ADC saluran maklumat adalah dari 300 mV ke 900 mV dengan voltan pertengahan pada 600 mV. Peringkat-peringkat saluran maklumat yang digunakan dalam pembinaan kedua-dua ADC saluran maklumat mengunakan litar Pendaraban Digital-ke-Analog Penukar (MDAC). Litar MDAC adalah berdasarkan kepada konfigurasi 1.5-bit suis-kapasitor dengan penguat kendalian (op-amp) pengamiran sepenuhnya yang mempunyai gandaan hampir 2. Pembetulan Ralat Digital (DEC) juga dicadangkan menggunakan kod Verilog-A pada dua blok, pengatur-masa dan penambah 4-bit. Tiada konsep pembetulan secara isyarat digunakan dalam litar tentukuran yang dicadangkan, membolehkan litar MDAC yang sama digunakan tanpa pengubahsuaian. Pejana palsu-rawak (PN) tidak digunakan dalam litar tentukuran yang dicadangkan. INL yang dicapai dengan tentukuran jenis litar 1 adalah dari maksimum 1 LSB ke minimum -1 LSB . Untuk tentukuran jenis litar 2 , INL yang dicapai adalah maksimum 1 LSB dan minimum 0 LSB . DNL yang dicapai dengan jenis 1 adalah dari maksimum 0 LSB ke minimum -1 LSB manakala jenis 2 mencapai 0 LSB . Two types (Type 1 and Type 2) of calibration circuits for the pipelined ADC was desgined using Verilog-A code modeling available from ahdlib Library of the Cadence Virtuoso tool. The modelling codes were modified to suit the proposed calibration circuit. Two identical pipelined ADC blocks (Pipelined ADC 1 and Pipelined ADC 2) were realized in 130nm Silterra CMOS process with each ADC having a 4-bit digital output respectively. A reference voltage of 600mV was used in the operation of the pipelined ADC with power supply connected to 1.2V for Vdd and ground GND for Vss. The pipelined ADC operates at a sampling frequency of 2.2727MHz with input frequency from DC to 1.1364MHz. The input range voltage of the pipelined ADC is 300mV to 900mV with common-mode voltage of 600mV. Stages used in the construction of each pipelined ADCs employed Multiplying Digital-to-Analog Converter (MDAC) circuit architecture. The MDAC circuit is based on the 1.5-bit switched capacitor configuration with fully-differential operational amplifier (op-amp) gain or radix of approximately 2. A Digital Error Correction (DEC) was also proposed using Verilog-A code modeling where two blocks, time-align block and 4-bit adder made up the DEC block. No dithering signal or concept was used in the proposed calibration circuit, enabling the same MDAC circuit to be used with no modifications. A DNL of 0 LSB was achieved when calibration was enabled. The INL achieved by Calibration circuit type 1 is from maximum +1 LSB to minimum -1 LSB. For the Calibration circuit type 2, INL achieved is maximum +1 LSB and minimum 0 LSB. The DNL achieved by type 1 is from maximum 0 LSB to minimum -1 LSB while type 2 achieved 0 LSB

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.MIT Barker Engineering Library copy: printed in pages.Also issued printed in pages.Includes bibliographical references (leaves 179-184).CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two complementary methods for addressing scaling issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called zero-crossing based circuits (ZCBC) that is more amenable to scaling trends. To demonstrate these circuits and algorithms, two different ADCs were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s in IBM 90nm technology. Together these techniques can be enabling technologies for both pipelined ADCs and general mixed signal design in deep sub-micron technologies.by Lane Gearle Brooks.Ph.D