876 research outputs found
Modelling of interconnects in 3DIC based on layered green functions
As traditional CMOS scaling pace gradually slows down, three-dimensional (3D) integration offers another dimension of in the ”More-than-Moore” era. In this dissertation, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs. Partial Element Equivalent Circuit (PEEC) method with layered Green’s function is studied here, since it consumes less computational resources and provides better physical insight to model the interconnects in 3DIC for high-speed digital circuits. The work is organized as a series of papers. The first paper reviewed the fundamental methods to derive layered Green’s function in spectral domain using discrete complex image method (DCIM) and analyzed the effects of each Green function terms to model silicon interconnects. The second paper proposed a unique method to extract poles near branch cut in complex kp plane, to accurately extract surface wave effects. The last paper proposed a new equivalent circuit model for coplanar waveguide (CPW) structure on 3DIC. The silicon effects on series inductance were also studied by employing the modified Green functions with semiconductor images at a complex distance from spectral-domain analysis. --Abstract, page iii
Delay Measurements and Self Characterisation on FPGAs
This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits
on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure
rate and transition probability is proposed for accurate, precise and efficient measurement of
propagation delays. The transition probability based method is especially attractive, since
it requires no modifications in the circuit-under-test and requires little hardware resources,
making it an ideal method for physical delay analysis of FPGA circuits.
The relentless advancements in process technology has led to smaller and denser transistors
in integrated circuits. While FPGA users benefit from this in terms of increased hardware
resources for more complex designs, the actual productivity with FPGA in terms of timing
performance (operating frequency, latency and throughput) has lagged behind the potential
improvements from the improved technology due to delay variability in FPGA components
and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure
delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation
and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA
designs.
The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for
cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability
problem in FPGAs
Using high resolution displays for high resolution cardiac data
The ability to perform fast, accurate, high resolution visualization is fundamental
to improving our understanding of anatomical data. As the volumes of data
increase from improvements in scanning technology, the methods applied to rendering
and visualization must evolve. In this paper we address the interactive display of
data from high resolution MRI scanning of a rabbit heart and subsequent histological
imaging. We describe a visualization environment involving a tiled LCD panel
display wall and associated software which provide an interactive and intuitive user
interface.
The oView software is an OpenGL application which is written for the VRJuggler
environment. This environment abstracts displays and devices away from the
application itself, aiding portability between different systems, from desktop PCs to
multi-tiled display walls. Portability between display walls has been demonstrated
through its use on walls at both Leeds and Oxford Universities. We discuss important
factors to be considered for interactive 2D display of large 3D datasets,
including the use of intuitive input devices and level of detail aspects
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