Computation of Conductance and Capacitance for IC Interconnects on a General Lossy Multilayer Substrate

In this paper a simple method for analysis and modelling of transmission interconnect lines on general lossy multilayer substrates at high bit rates is presented. The analysis is based on semi-analytical Green's function approach and recurrence relation between the coefficients of potential in n and n + 1 layers, respectively. The electromagnetic concept of free charge density is applied. It allows us to obtain integral equations between electric scalar potential and charge density distributions. These equations are solved by the Galerkin procedure of the Method of Moments. New approach is especially adequate to model 2-D layered structures with planar boundaries for frequencies up to 20GHz (quasistationary field approach). The transmission line parameters (capacitance and conductance per unit length) for the given interconnect multilayer geometry are computed. A discussion of the calculated line admittance in terms of technological and geometrical parameters of the structure is given. A comparison of the numerical results from the new procedure with the techniques presented in the previous publications are provided, too

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

3D Capacitance Extraction With the Method of Moments

In this thesis, the Method of Moments has been applied to calculate capacitance between two arbitrary 3D metal conductors or a capacitance matrix for a 3D multi-conductor system. Capacitance extraction has found extensive use for systems involving sets of long par- allel transmission lines in multi-dielectric environment as well as integrated circuit package including three-dimensional conductors located on parallel planes. This paper starts by reviewing fundamental aspects of transient electro-magnetics followed by the governing dif- ferential and integral equations to motivate the application of numerical methods as Method of Moments(MoM), Finite Element Method(FEM), etc. Among these numerical tools, the surface-based integral-equation methodology - MoM is ideally suited to address the prob- lem. It leads to a well-conditioned system with reduced size, as compared to volumetric methods. In this dissertation, the MoM Surface Integral Equation (SIE)-based modeling approach is developed to realize electrostatic capacitance extraction for 3D geometry. MAT- LAB is employed to validate its e?ciency and e?ectiveness along with design of a friendly GUI. As a base example, a parallel-plate capacitor is considered. We evaluate the accu- racy of the method by comparison with FEM simulations as well as the corresponding quasi-analytical solution. We apply this method to the parallel-plate square capacitor and demonstrate how far could the undergraduate result 0C = A ? =d\u27 be from reality. For the completion of the solver, the same method is applied to the calculation of line capacitance for two- and multi-conductor 2D transmission lines

Accurate electromagnetic full-wave modeling for interconnects in semiconductor integrated circuits

Semiconductor-based integrated circuits have become the mainstream for very-large-scale integration systems such as high-speed digital circuits, radio-frequency integrated circuits, and even monolithic microwave integrated circuits. The shrinking feature size and increasing frequency promote high integration density and interconnection complexity that demand high-accuracy modeling techniques. The current design paradigm has shifted from the transistor-driven design to the interconnect-driven design. Thus the accurate electromagnetic full-wave modeling of on-chip interconnect becomes critical for the computer-aided design tools to analyze the overall system performance.;In this research, the full-wave spectral domain approach is implemented to investigate the electromagnetic properties of multilayered transmission lines with semiconductor substrates. In particular, finite thin metallization components, such as the thin metal ground layer and signal strips, are focused on. The thin metal ground layer is generally designed as a shield or a ground plane to depress the coupling and noise from neighboring components. But its fabricated thickness is often a small fraction of one micron, which may allow electromagnetic fields to penetrate through at some low frequencies. Such electromagnetic leakage phenomena play a significant role in the overall dispersive performance of transmission lines, and their consideration is inevitable.;For the spectral domain approach, the metallization layer can be rigorously modeled as a dielectric with a complex permittivity. However, due to the large conductivity of metal, the conventional transfer matrix method has potential overflow problems in obtaining the multilayered Green\u27s function. In our research, a new formulation of the cascaded matrix is developed to overcome such numerical difficulties. Based on this formulation, the complete characteristics of multilayered transmission lines with thin metallization components are studied by parameters like the propagation constant, attenuation per unit length, field distribution, characteristic impedance, transient response, and extracted resistance, inductance, capacitance, and conductance of equivalent circuits. The parallel-plate waveguide model is applied to study a metal-insulator-metal-semiconductor structure. The first- and second-order low-frequency approximations for the fundamental propagation mode are derived with corresponding equivalent circuit models. In addition, other approximate models for the thin metal ground are compared numerically to assess their validity.;Two transmission lines with the metal-insulator-metal-semiconductor and the metal-insulator-metal-insulator structures are analyzed. Numerical results indicate that the thin metallization components have significant impacts on the propagation characteristics. The thin metal layer can enhance or even excite the slow-wave mode. Thus, it is necessary to take these effects into account to achieve accurate and reliable analysis of integrated circuit interconnects from dc to millimeter-wave frequencies

Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Ph.DDOCTOR OF PHILOSOPH

High-Performance Computing for the Electromagnetic Modeling and Simulation of Interconnects

The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In recent years, packaging has become a critical area in the design of high-speed communication systems and fast computers, and the importance of the software support for their development has increased accordingly. Throughout this project, our efforts have focused on the development of modeling and simulation techniques and algorithms that permit the fast computation of the electrical parameters of interconnects and the efficient simulation of their electrical performance

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Application of Maxwell-Wagner polarisation in monolithic technologies

Imperial Users onl

Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications

The complexity of chip interconnection on a multicore multichip (MCMC) module using the traditional wired interconnects increases with the chip count. The global wired interconnects that run across the entire module must be made longer as more chips are placed on a larger module. Since the interconnect delay grows as the square of the interconnect length, the global wired interconnects can become a major bottleneck of the computing performance in such systems. This dissertation presents a new type of hybrid space-surface wave interconnect (HSSW-I) using 60 GHz switched-beam antenna arrays to provide high-speed communication between the chips. The antennas communicate at near the speed of light through radiation in the air above the chips and through surface waves at the air-dielectric interface, and thus avoid lengthy delays. Each array consists of four center-fed circular patch elements with side vias in a 2 × 2 planar grid arrangement. The arrays enable multi-gigabits-per-second (Gbps) reconfigurable interchip communication when integrated with the proper chip transceivers. The main beam of the array is switched in the horizontal plane containing the chips, by changing the interelement phase shifts. The switching of the main beam is analyzed and verified through full-wave simulation. A compact two-dimensional (2-D) Butler matrix feed network is designed, implemented, and integrated with the circular patch planar array. The matrix is a four-input, four-output, i.e., 4 × 4 network consisting of four interconnected quadrature (90°) hybrid couplers and allows endfire scanning of the array main beam along the four diagonal directions in the horizontal plane. The realized antenna module is a thin multilayer microstrip (MS) structure with a footprint small enough to fit over a typical multicore chip. The antenna module provides a seamless and practical way to achieve reconfigurable interchip communication in MCMC systems. A multiantenna module (MAM) consisting of five antenna modules that emulates diagonal interchip communication in MCMC systems is fabricated. The simulation and measurement of the transmission coefficients between the antenna modules on the MAM are performed, and the signal-to-noise ratio (SNR) and signal-to-noise-plus-interference ratio (SNIR) of the links are calculated. A link decomposition simulation technique to determine the relative contribution of space and surface waves is also applied. A transmission link model is devised based on the leaky wave effect shown by the antenna arrays and the model coefficients are determined from the simulation data. The link model is then extrapolated at various distances and compared with more measurement and simulation results for verification. Finally, realistic link budget calculations are performed based on the measured and simulated data. The calculations show that the antenna modules using the HSSW-I can achieve raw data transfer rates up to 42.24 Gbps at 20 mm distance with low bit error rates (BERs) in the absence of interference, when used with the state-of-the-art 60 GHz complementary metal oxide semiconductor (CMOS) transceivers