Fast and Flexible Software Polar List Decoders

Flexibility is one mandatory aspect of channel coding in modern wireless communication systems. Among other things, the channel decoder has to support several code lengths and code rates. This need for flexibility applies to polar codes that are considered for control channels in the future 5G standard. This paper presents a new generic and flexible implementation of a software Successive Cancellation List (SCL) decoder. A large set of parameters can be fine-tuned dynamically without re-compiling the software source code: the code length, the code rate, the frozen bits set, the puncturing patterns, the cyclic redundancy check, the list size, the type of decoding algorithm, the tree-pruning strategy and the data quantization. This generic and flexible SCL decoder enables to explore tradeoffs between throughput, latency and decoding performance. Several optimizations are proposed to achieve a competitive decoding speed despite the constraints induced by the genericity and the flexibility. The resulting polar list decoder is about 4 times faster than a generic software decoder and only 2 times slower than a non-flexible unrolled decoder. Thanks to the flexibility of the decoder, the fully adaptive SCL algorithm can be easily implemented and achieves higher throughput than any other similar decoder in the literature (up to 425 Mb/s on a single processor core for N = 2048 and K = 1723 at 4.5 dB).Comment: 11 pages, 7 figures, submitted to Springer Journal of Signal Processing System

Fast and Flexible Software Polar List Decoders

International audienceFlexibility is one mandatory aspect of channel coding in modern wireless communication systems. Among other things, the channel decoder has to support several code lengths and code rates. This need for flexibility applies to polar codes that are considered for control channels in the future 5G standard. This paper presents a new generic and flexible implementation of a software Successive Cancellation List (SCL) decoder. A large set of parameters can be fine-tuned dynamically without re-compiling the software source code: the code length, the code rate, the frozen bits set, the puncturing patterns, the cyclic redundancy check, the list size, the type of decoding algorithm, the tree-pruning strategy and the data quantization. This generic and flexible SCL decoder enables to explore tradeoffs between throughput, latency and decoding performance. Several optimizations are proposed to achieve a competitive decoding speed despite the constraints induced by the genericity and the flexibility. The resulting polar list decoder is about 4 times faster than a generic software decoder and only 2 times slower than a non-flexible unrolled decoder. Thanks to the flexibility of the decoder, the fully adaptive SCL algorithm can be easily implemented and achieves higher throughput than any other similar decoder in the literature (up to 425 Mb/s on a single processor core for N = 2048 and K = 1723 at 4.5 dB)

An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes

In theory, Polar codes do not exhibit an error floor under successive-cancellation (SC) decoding. In practice, frame error rate (FER) down to $10^{-12}$ has not been reported with a real SC list (SCL) decoder hardware. This paper presents an asymmetric adaptive SCL (A2SCL) decoder, implemented in real hardware, for high-throughput and ultra-reliable communications. We propose to concatenate multiple SC decoders with an SCL decoder, in which the numbers of SC/SCL decoders are balanced with respect to their area and latency. In addition, a novel unequal-quantization technique is adopted. The two optimizations are crucial for improving SCL throughput within limited chip area. As an application, we build a link-level FPGA emulation platform to measure ultra-low FERs of 3GPP NR Polar codes (with parity-check and CRC bits). It is flexible to support all list sizes up to $8$, code lengths up to $1024$ and arbitrary code rates. With the proposed hardware, decoding speed is 7000 times faster than a CPU core. For the first time, FER as low as $10^{-12}$ is measured and quantization effect is analyzed

On Error-Correction Performance and Implementation of Polar Code List Decoders for 5G

Polar codes are a class of capacity achieving error correcting codes that has been recently selected for the next generation of wireless communication standards (5G). Polar code decoding algorithms have evolved in various directions, striking different balances between error-correction performance, speed and complexity. Successive-cancellation list (SCL) and its incarnations constitute a powerful, well-studied set of algorithms, in constant improvement. At the same time, different implementation approaches provide a wide range of area occupations and latency results. 5G puts a focus on improved error-correction performance, high throughput and low power consumption: a comprehensive study considering all these metrics is currently lacking in literature. In this work, we evaluate SCL-based decoding algorithms in terms of error-correction performance and compare them to low-density parity-check (LDPC) codes. Moreover, we consider various decoder implementations, for both polar and LDPC codes, and compare their area occupation and power and energy consumption when targeting short code lengths and rates. Our work shows that among SCL-based decoders, the partitioned SCL (PSCL) provides the lowest area occupation and power consumption, whereas fast simplified SCL (Fast-SSCL) yields the lowest energy consumption. Compared to LDPC decoder architectures, different SCL implementations occupy up to 17.1x less area, dissipate up to 7.35x less power, and up to 26x less energy.Comment: Accepted in 55th Annual Allerton Conference on Communication, Control, and Computin

A Complexity Reduction Method for Successive Cancellation List Decoding

This brief introduces a hardware complexity reduction method for successive cancellation list (SCL) decoders. Specifically, we propose to use a sorting scheme so that L paths with smallest path metrics are also sorted according to their path indexes for path pruning. We prove that such sorting scheme reduces the input number of multiplexers in any hardware implementation of SCL decoding from L to (L/2+1) without any changes in the decoding latency. We also propose sorter architectures for the proposed sorting method. Field programmable gate array (FPGA) implementations show that the proposed method achieves significant gain in hardware consumptions of SCL decoder implementations, especially for large list sizes and block lengths.Comment: 6 pages, 3 figures, 6 table

Fast and Flexible Successive-Cancellation List Decoders for Polar Codes

Polar codes have gained significant amount of attention during the past few years and have been selected as a coding scheme for the next generation of mobile broadband standard. Among decoding schemes, successive-cancellation list (SCL) decoding provides a reasonable trade-off between the error-correction performance and hardware implementation complexity when used to decode polar codes, at the cost of limited throughput. The simplified SCL (SSCL) and its extension SSCL-SPC increase the speed of decoding by removing redundant calculations when encountering particular information and frozen bit patterns (rate one and single parity check codes), while keeping the error-correction performance unaltered. In this paper, we improve SSCL and SSCL-SPC by proving that the list size imposes a specific number of bit estimations required to decode rate one and single parity check codes. Thus, the number of estimations can be limited while guaranteeing exactly the same error-correction performance as if all bits of the code were estimated. We call the new decoding algorithms Fast-SSCL and Fast-SSCL-SPC. Moreover, we show that the number of bit estimations in a practical application can be tuned to achieve desirable speed, while keeping the error-correction performance almost unchanged. Hardware architectures implementing both algorithms are then described and implemented: it is shown that our design can achieve 1.86 Gb/s throughput, higher than the best state-of-the-art decoders.Comment: IEEE Transactions on Signal Processin

High Throughput Polar Decoding Using Two-Staged Adaptive Successive Cancellation List Decoding

Polar codes are the first class of capacity-achieving forward error correction (FEC) codes. They have been selected as one of the coding schemes for the 5G communication systems due to their excellent error correction performance when successive cancellation list (SCL) decoding with cyclic redundancy check (CRC) is used. A large list size is necessary for SCL decoding to achieve a low error rate. However, it impedes SCL decoding from achieving a high throughput as the computational complexity is very high when a large list size is used. In this paper, we propose a two-staged adaptive SCL (TA-SCL) decoding scheme and the corresponding hardware architecture to accelerate SCL decoding with a large list size. Constant system latency and data rate are supported by TA-SCL decoding. To analyse the decoding performance of TA-SCL, an accurate mathematical model based on Markov Chain is derived, which can be used to determine the parameters for practical designs. A VLSI architecture implementing TA-SCL decoding is then proposed. The proposed architecture is implemented using UMC 90nm technology. Experimental results show that TA-SCL can achieve throughputs of 3.00 and 2.35 Gbps when the list sizes are 8 and 32, respectively, which are nearly 3 times as that of the state-ofthe-art SCL decoding architectures, with negligible performance degradation on a wide signal-to-noise ratio (SNR) range and small hardware overhead.Comment: 12 pages, 12 figures, 7 tables, Submitted to IEEE Transactions on Circuits and Systems I: Regular Paper

A Two-staged Adaptive Successive Cancellation List Decoding for Polar Codes

Polar codes achieve outstanding error correction performance when using successive cancellation list (SCL) decoding with cyclic redundancy check. A larger list size brings better decoding performance and is essential for practical applications such as 5G communication networks. However, the decoding speed of SCL decreases with increased list size. Adaptive SCL (ASCL) decoding can greatly enhance the decoding speed, but the decoding latency for each codeword is different so A-SCL is not a good choice for hardware-based applications. In this paper, a hardware-friendly two-staged adaptive SCL (TA-SCL) decoding algorithm is proposed such that a constant input data rate is supported even if the list size for each codeword is different. A mathematical model based on Markov chain is derived to explore the bounds of its decoding performance. Simulation results show that the throughput of TA-SCL is tripled for good channel conditions with negligible performance degradation and hardware overhead.Comment: 5 pages, 7 figures, 1 table. Accepted by ISCAS 201

A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

We consider practical hardware implementation of Polar decoders. To reduce latency due to the serial nature of successive cancellation (SC), existing optimizations improve parallelism with two approaches, i.e., multi-bit decision or reduced path splitting. In this paper, we combine the two procedures into one with an error-pattern-based architecture. It simultaneously generates a set of candidate paths for multiple bits with pre-stored patterns. For rate-1 (R1) or single parity-check (SPC) nodes, we prove that a small number of deterministic patterns are required to guarantee performance preservation. For general nodes, low-weight error patterns are indexed by syndrome in a look-up table and retrieved in O(1) time. The proposed flip-syndrome-list (FSL) decoder fully parallelizes all constituent code blocks without sacrificing performance, thus is suitable for ultra-low-latency applications. Meanwhile, two code construction optimizations are presented to further reduce complexity and improve performance, respectively.Comment: 10 pages, submitted to IEEE Access (Special Issue on Advances in Channel Coding for 5G and Beyond

Hardware Implementation of Fano Decoder for PAC Codes

This paper proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture maintains a trade-off between the error-correction performance and throughput of the decoder by implementing tree search constraining methods. The performance of the proposed decoder is evaluated on FPGA and ASIC using Xilinx Nexys 4 Artix-7 and TSMC 28 nm 0.72 V library, respectively. The PAC decoder can be clocked at 400 MHz and reach an average information throughput of 15.10 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and code rate of 1/2