Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin Sean; Committee Member: Mukhopadhyay, Saiba

Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts

The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Mukhopadhyay, Saibal; Committee Member: Swaminathan, Madhava

Macro-model of through silicon vias (tsvs) arrays

As continued scaling down of transistors becomes increasingly difficult due to physical and technical issues like the increase of leakage power and total power consumption, overall, 3D integration is now considered a viable solution to get a higher bandwidth and power efficiency. Use of Through-silicon-vias (TSVs), which connects stacked structures die-to-die, is expected to be one of the most important techniques enabling 3D integration. As the number of through silicon Vias (TSVs) exists in the same chip is increasing, an algorithm to build a macro-model is needed to find inter-relationship between TSVs. There are different coupling parameters that exist between TSVs like: capacitive, inductive and resistive coupling. This work provides an algorithm to build a macro-model of an array of TSVs where only capacitive coupling is considered, as it is expected to be the dominating parameter.Using a simulation based technique, where characterization for bundles of TSVs were done and a scaling equation that can give the variationsoccur to capacitance value with scaling the physical dimensions of the TSV (pitch, radius, length and dielectric thickness (tox)) is proposed. The considered ranges for the physical parameters are: radius (from 1um to 10um), tox (from 0.1um to 0.5 um), length (from 10um to 100um) and pitch (from 10um to 95um). Using theproposed algorithm, a macro model can be built in a negligible time, which provides lots of time saving compared to hours required by other tools such as EM simulators or device simulators. The average error range 3% to 6%and a maximum cumulative error of algorithm and usage of scaling equation is 18.2% that occurs at very few dimensions and in very few capacitances from the extracted capacitance values, for both self and coupling capacitance

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

3D modeling and integration of current and future interconnect technologies

Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit performance and signal integrity in the circuit design phase. A full phase simulation for performance estimation of a large-scale circuit not only require a massive computational resource but also need a lot of time to produce acceptable results. The estimation of performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect capacitance. So, an accurate model for interconnect capacitance can be used in the circuit CAD (computer-aided design) tools for circuit performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the interconnect lines. Closed-form equations have been derived analytically for ground and coupling capacitance. First, the capacitance model for a single line is developed, and then the new model is used to derive expressions for the capacitance of a line surrounded by neighboring lines in the same and the adjacent layers above and below. These expressions are simple, and the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias. Signal speed in current digital systems depends mainly on the delay of interconnects. To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit (vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to ensure much smaller interconnect lengths, and lower delay and power consumption compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit performance depends on different electrical parameters (capacitance, resistance, inductance) of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance, resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived from the physical shape and the size of the TSV. The modeling approach is comprehensive and includes both the cylindrical and tapered TSVs as well as the bumps. On-chip integration of inductors has always been very challenging. However, for sub- 14nm on-chip applications, large area overhead imposed by the on-chip capacitors and inductors has become a more severe concern. To overcome this issue and ensure power integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The proposed TSV based inductor has the potential to achieve both high density and high performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV based inductor is also presented. The implementation of the VCO is intended to study the feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor

Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs

Abstract-In 3D ICs, block-level designs provide various advantages over designs done at other granularity such as gate-level because they promote the reuse of IP blocks. In this paper, we study block-level 3D-IC designs, where the footprint of the dies in the stack are different. This happens in case of die-to-wafer bonding, which is more popular choice for near-term low-cost 3D designs. We study design quality tradeoffs among three different ways to place through-silicon vias (TSVs): TSV-farm, TSV-distributed, and TSV-whitespace. In our holistic approach, we use wirelength, power, performance, temperature, and mechanical stress metrics to conduct comprehensive comparative studies on the three design styles. In addition, we provide analysis on the impact of TSV size and pitch on the design quality of these three styles

Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits

This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology