ADC Nonlinearity Correction for the Majorana Demonstrator

Imperfections in analog-to-digital conversion (ADC) cannot be ignored when signal digitization requirements demand both wide dynamic range and high resolution, as is the case for the Majorana Demonstrator 76Ge neutrinoless double-beta decay search. Enabling the experiment's high-resolution spectral analysis and efficient pulse shape discrimination required careful measurement and correction of ADC nonlinearities. A simple measurement protocol was developed that did not require sophisticated equipment or lengthy data-taking campaigns. A slope-dependent hysteresis was observed and characterized. A correction applied to digitized waveforms prior to signal processing reduced the differential and integral nonlinearities by an order of magnitude, eliminating these as dominant contributions to the systematic energy uncertainty at the double-beta decay Q value

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

SPHERE: the exoplanet imager for the Very Large Telescope

Observations of circumstellar environments to look for the direct signal of exoplanets and the scattered light from disks has significant instrumental implications. In the past 15 years, major developments in adaptive optics, coronagraphy, optical manufacturing, wavefront sensing and data processing, together with a consistent global system analysis have enabled a new generation of high-contrast imagers and spectrographs on large ground-based telescopes with much better performance. One of the most productive is the Spectro-Polarimetic High contrast imager for Exoplanets REsearch (SPHERE) designed and built for the ESO Very Large Telescope (VLT) in Chile. SPHERE includes an extreme adaptive optics system, a highly stable common path interface, several types of coronagraphs and three science instruments. Two of them, the Integral Field Spectrograph (IFS) and the Infra-Red Dual-band Imager and Spectrograph (IRDIS), are designed to efficiently cover the near-infrared (NIR) range in a single observation for efficient young planet search. The third one, ZIMPOL, is designed for visible (VIR) polarimetric observation to look for the reflected light of exoplanets and the light scattered by debris disks. This suite of three science instruments enables to study circumstellar environments at unprecedented angular resolution both in the visible and the near-infrared. In this work, we present the complete instrument and its on-sky performance after 4 years of operations at the VLT.Comment: Final version accepted for publication in A&

Gemini multi-conjugate adaptive optics system review II: Commissioning, operation and overall performance

The Gemini Multi-conjugate Adaptive Optics System - GeMS, a facility instrument mounted on the Gemini South telescope, delivers a uniform, near diffraction limited images at near infrared wavelengths (0.95 microns- 2.5 microns) over a field of view of 120 arc seconds. GeMS is the first sodium layer based multi laser guide star adaptive optics system used in astronomy. It uses five laser guide stars distributed on a 60 arc seconds square constellation to measure for atmospheric distortions and two deformable mirrors to compensate for it. In this paper, the second devoted to describe the GeMS project, we present the commissioning, overall performance and operational scheme of GeMS. Performance of each sub-system is derived from the commissioning results. The typical image quality, expressed in full with half maximum, Strehl ratios and variations over the field delivered by the system are then described. A discussion of the main contributor to performance limitation is carried-out. Finally, overheads and future system upgrades are described.Comment: 20 pages, 11 figures, accepted for publication in MNRA

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB

Error Compensation in Pipeline and Converters

This thesis provides an improved calibration and compensation scheme for pipeline Analog-to-Digital Converters (ADCs). This new scheme utilizes the intermediate stage outputs in a pipeline to characterize error mechanisms in the architecture. The goal of this compensation scheme is to increase the dynamic range of the ADC. The pipeline architecture is described in general, and tailored to the 1.5 bitslstage topology. Dominant error mechanisms are defined and characterized for an arbitrary stage in the pipeline. These error mechanisms are modeled with basis functions. The traditional calibration scheme is modified and used to iteratively calculate the error characteristics. The information from calibration is used to compensate the ADC. The calibration and compensation scheme is demonstrated both in simulation and using a custom hardware pipeline ADC. A 10-bit 5 MHz ADC was designed and fabricated in 0.5 pm CMOS to serve as the demonstration platform. The scheme was successful in showing improvements in dynamic range while using intermediate stage outputs to efficiently model errors in a pipeline stage. An application of the technique on the real converter showed an average of 8.6 dB improvement in SFDR in the full Nyquist band of the ADC. The average improvement in SINAD and ENOB are 3.2 dB and 0.53 bits respectively