Magnetic Cellular Nonlinear Network with Spin Wave Bus for Image Processing

We describe and analyze a cellular nonlinear network based on magnetic nanostructures for image processing. The network consists of magneto-electric cells integrated onto a common ferromagnetic film - spin wave bus. The magneto-electric cell is an artificial two-phase multiferroic structure comprising piezoelectric and ferromagnetic materials. A bit of information is assigned to the cell's magnetic polarization, which can be controlled by the applied voltage. The information exchange among the cells is via the spin waves propagating in the spin wave bus. Each cell changes its state as a combined effect of two: the magneto-electric coupling and the interaction with the spin waves. The distinct feature of the network with spin wave bus is the ability to control the inter-cell communication by an external global parameter - magnetic field. The latter makes possible to realize different image processing functions on the same template without rewiring or reconfiguration. We present the results of numerical simulations illustrating image filtering, erosion, dilation, horizontal and vertical line detection, inversion and edge detection accomplished on one template by the proper choice of the strength and direction of the external magnetic field. We also present numerical assets on the major network parameters such as cell density, power dissipation and functional throughput, and compare them with the parameters projected for other nano-architectures such as CMOL-CrossNet, Quantum Dot Cellular Automata, and Quantum Dot Image Processor. Potentially, the utilization of spin waves phenomena at the nanometer scale may provide a route to low-power consuming and functional logic circuits for special task data processing

Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT’s connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-µm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 µW/unit and image processing times below 2 µs

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Determination of Aggregate Elastic Properties of Powder-Beds in Additive Manufacturing Using Convolutional Neural Networks

The most popular strategy for the estimation of effective elastic properties of powder-beds in Additively Manufactured structures (AM structures) is through either the Finite Element Method (FEM) or the Discrete Element Method (DEM). Both of these techniques, however, are computationally expensive for practical applications. This paper presents a novel Convolutional Neural Network (CNN) regression approach to estimate the effective elastic properties of powder-beds in AM structures. In this approach, the time-consuming DEM is used for CNN training purposes and not at run time. The DEM is used to model the interactions of powder particles and to evaluate the macro-level continuum-mechanical state variables (volume average of stress and strain). For the Neural Network training purposes, the DEM code creates a dataset, including hundreds of AM structures with their corresponding mechanical properties. The approach utilizes methods from deep learning to train a CNN capable of reducing the computational time needed to predict the effective elastic properties of the aggregate. The saving in computational time could reach 99.9995% compared to DEM, and on average, the difference in predicted effective elastic properties between the DEM code and trained CNN is less than 4%. The resulting sub-second level computational time can be considered as a step towards the development of a near real-time process control system capable of predicting the effective elastic properties of the aggregate at any given stage of the manufacturing process

PDN modeling for high-speed multilayer PCB boards and decap optimization using machine learning techniques

In power distribution networks (PDN), there are two main challenges nowadays. One challenge is how to efficiently model and calculate the impedance for arbitrary-shape and multi-layer PDN systems. The second challenge is the optimization of decoupling capacitors in the pre-layout stage. This dissertation proposes novel solutions to these two challenges. To tackle the first challenge, a boundary element method (BEM) is utilized to calculate the quasi-static inductances between vertical vias for arbitrary-shape planes. Then a specialized circuit solver is developed to solve the equivalent circuit of inductances and capacitances for multi-layer PDN structures. Also, a contour integral method (CIM) is used to calculate the DC IR drop. Therefore, both DC and AC impedance can be calculated very efficiently. Afterward, over one million printed circuit boards (PCBs) are generated with different board shapes, stackups, IC location, and decap placement. A deep learning model is trained with the generated data to predict the impedance for any new board using just 0.1 seconds. What’s more, deep reinforcement learning (DRL) is adopted to accelerate the decap optimization process. Large amounts of PCBs with different shapes, stackups, IC location, VRM location, and decap locations are generated and used to train a DRL model. The trained DRL can predict a near-optimal solution to satisfy a target impedance for any new board that has not been used for training within 0.1 seconds. Then the solution is fed to a genetic algorithm (GA) as a seed solution, which can greatly reduce the search time for the GA. The modeling method and the machine learning techniques proposed in this work are novel and valuable to the efficiency improvement of pre-layout decap optimization and post-layout performance evaluation for PDN systems --Abstract, page iv

Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin