1,637 research outputs found
A Chaotic IP Watermarking in Physical Layout Level Based on FPGA
A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented. An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as specific functions when it is placed and routed onto the FPGA (Field-Programmable Gate Array). The main contribution is the use of multiple chaotic maps in the processes of watermark design and embedding, which efficiently improves the security of watermark. A hashed chaotic sequence is used to scramble the watermark. Secondly, two pseudo-random sequences are generated by using chaotic maps. One is used to determine unused LUT locations, and the other divides the watermark into groups. The watermark identifies original owner and is difficult to detect. This scheme was tested on a Xilinx Virtex XCV600-6bg432 FPGA. The experimental results show that our method has low impact on functionality, short path delay and high robustness in comparison with other methods
Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices
Protecting intellectual property (IP) in electronic circuits has become a
serious challenge in recent years. Logic locking/encryption and layout
camouflaging are two prominent techniques for IP protection. Most existing
approaches, however, particularly those focused on CMOS integration, incur
excessive design overheads resulting from their need for additional circuit
structures or device-level modifications. This work leverages the innate
polymorphism of an emerging spin-based device, called the giant spin-Hall
effect (GSHE) switch, to simultaneously enable locking and camouflaging within
a single instance. Using the GSHE switch, we propose a powerful primitive that
enables cloaking all the 16 Boolean functions possible for two inputs. We
conduct a comprehensive study using state-of-the-art Boolean satisfiability
(SAT) attacks to demonstrate the superior resilience of the proposed primitive
in comparison to several others in the literature. While we tailor the
primitive for deterministic computation, it can readily support stochastic
computation; we argue that stochastic behavior can break most, if not all,
existing SAT attacks. Finally, we discuss the resilience of the primitive
against various side-channel attacks as well as invasive monitoring at runtime,
which are arguably even more concerning threats than SAT attacks.Comment: Published in Proc. Design, Automation and Test in Europe (DATE) 201
New Family of Stream Ciphers as Physically Clone-Resistant VLSI-Structures
A new large class of possible stream ciphers as keystream
generators KSGs, is presented. The sample cipher-structure-concept is based on
randomly selecting a set of 16 maximum-period Nonlinear Feedback Shift
Registers (NLFSRs). A non-linear combining function is merging the 16 selected
sequences. All resulting stream ciphers with a total state-size of 223 bits are
designed to result with the same security level and have a linear complexity
exceeding and a period exceeding . A Secret Unknown Cipher
(SUC) is created randomly by selecting one cipher from that class of
ciphers. SUC concept was presented recently as a physical security anchor to
overcome the drawbacks of the traditional analog Physically Unclonable
Functions (PUFs). Such unknown ciphers may be permanently self-created within
System-on-Chip SoC non-volatile FPGA devices to serve as a digital
clone-resistant structure. Moreover, a lightweight identification protocol is
presented in open networks for physically identifying such SUC structures in
FPGA-devices. The proposed new family may serve for lightweight realization of
clone-resistant identities in future self-reconfiguring SoC non-volatile FPGAs.
Such self-reconfiguring FPGAs are expected to be emerging in the near future
smart VLSI systems. The security analysis and hardware complexities of the
resulting clone-resistant structures are evaluated and shown to exhibit
scalable security levels even for post-quantum cryptography.Comment: 24 pages, 7 Figures, 3 Table
VLSI Design IP Protection: Solutions, New Challenges, and Opportunities
It has been a decade since the need of VLSI design
intellectual property (IP) protection was identified
[1,2]. The goals of IP protection are 1) to enable IP
providers to protect their IPs against unauthorized
use, 2) to protect all types of design data used to
produce and deliver IPs, 3) to detect the use of IPs,
and 4) to trace the use of IPs [3]. There are significant
advances from both industry and academic towards
these goals. However, do we have solutions to achieve
all these goals? What are the current state-of-the-art
IP protection techniques? Do they meet the protection
requirement designers sought for? What are the (new)
challenges and is there any feasible answer to them in
the foreseeable future?
This paper addresses these questions and provides
possible solutions mainly from academia point of
view. Several successful industry practice and ongoing
efforts are also discussed briefly
Automatic low-cost IP watermarking technique based on output mark insertions
International audienceToday, although intellectual properties (IP) and their reuse are common, their use is causing design security issues: illegal copying, counterfeiting, and reverse engineering. IP watermarking is an efficient way to detect an unauthorized IP copy or a counterfeit. In this context, many interesting solutions have been proposed. However, few combine the watermarking process with synthesis. This article presents a new solution, i.e. automatic low cost IP watermarking included in the high-level synthesis process. The proposed method differs from those cited in the literature as the marking is not material, but is based on mathematical relationships between numeric values as inputs and outputs at specified times. Some implementation results with Xilinx Virtex-5 FPGA that the proposed solution required a lower area and timing overhead than existing solutions
Publicly Detectable Watermarking for Intellectual Property Authentication in VLSI Design
Highlighted with the newly released intellectual property
(IP) protection white paper by VSI Alliance, the protection of virtual
components or IPs in very large scale integration (VLSI) design has
received a great deal of attention recently. Digital signature/watermark
is one of the most promising solutions among the known protection
mechanisms. It provides desirable proof of authorship without rendering
the IP useless. However, it makes the watermark detection, which is as
important as watermarking, an NP-hard problem. In fact, the tradeoff between
hard-to-attack and easy-to-detect and the lack of efficient detection
schemes are the major obstacles for digital signatures to thrive. In this
paper, the authors propose a new watermarking method which allows the
watermark to be publicly detected without losing its strength and security.
The basic idea is to create a cryptographically strong pseudo-random
watermark, embed it into the original problem as a special (which the
authors call mutual exclusive) constraint, and make it public. The authors
combine data integrity technique and the unique characteristics in the
design of VLSI IPs such that adversaries will not gain any advantage from
the public watermarking for forgery. This new technique is compatible
with the existing constraint-based watermarking/fingerprinting techniques.
The resulting public–private watermark maintains the strength of
a watermark and provides easy detectability with little design overhead.
The authors build the mathematical framework for this approach based
on the concept of mutual exclusive constraints. They use popular VLSI
CAD problems, namely technology mapping, partitioning, graph coloring,
FPGA design, and Boolean satisfiability, to demonstrate the public
watermark’s easy detectability, high credibility, low design overhead, and
robustness
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