180 research outputs found

    AN EXTENDED GREEN-SASAO HIERARCHY OF CANONICAL TERNARY GALOIS FORMS AND UNIVERSAL LOGIC MODULES

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    A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valuedShannon and Davio spectral transforms.   

    Combinational logic synthesis based on the dual form of Reed-Muller representation

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    In certain applications, AND/XOR (Reed-Muller), and ORlXNOR (Dual form of Reed-Muller) logic have shown some attractive advantages over the standard Sum of Products (SOP) and Product of Sums (POS). Bidirectional conversion algorithms between SOP and AND/XOR also between POS and ORlXNOR based on Sparse and partitioning techniques are presented for multiple output Boolean functions. The developed programs are tested for some benchmarks with up to 20 inputs and 40 outputs. A new direct method is presented to calculate the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) from the truth vector of the POS. Any Boolean function can be expressed by FPDRM forms. There are 211 polarities for an n-variable function and the number of sum terms depends on these polarities. Finding the best polarity is costly interims of CPU time, in order to search for the best polarity which will lead to the minimum number of sums for a particular function. Therefore, an algorithm is developed to compute all the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) with polarity p from any polarity q. This technique is used to find the best polarity of FPDRM among the 211 fixed polarities. The algorithm is based on the Dual- polarity property and the Gray code strategy. Therefore, there is no need to start from POS form to find FPDRM coefficients for all the polarities. The proposed methods are efficient in terms of memory size and CPU time. A fast algorithm is developed and implemented in C language which can convert between POSs and FPDRMs. The program was tested for up to 23 variables. A modified version of the same program was used to find the best polarity. For up to 13 variables the CPU time was less than 42 seconds. To search for the optimal polarity for large number of variables and to reduce the se arch time 0 ffinding the 0 ptimal polarity 0 fthe function, two new algorithms are developed and presented in this thesis. The first one is used to convert between P OS and Positive Polarity Dual Reed-Muller (PPDRM) forms. The second algorithm will find the optimal fixed polarity for the FPDRM among the 211 different polarities for large n-variable functions. The most popular minimization criterion of the FPDRM form is obtained by the exhaustive search of the entire polarity vector. A non-exhaustive method for FPDRM expansions is presented. The new algorithms are based on separation of the truth vector (T) of POSs around each variable Xi into two groups. Instead of generating all of the polarity sets and searching for the best polarity, this algorithm will find the optimal polarity using the separation and sparse techniques, which will lead to optimal polarity. Time efficiency and computing speed are thus achieved in this technique. The algorithms don't require a large size of memory and don't require a long CPU time. The two algorithms are implemented in C language and tested for some benchmark. The proposed methods are fast and efficient as shown in the experimental results and can be used for large number of variables.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    Combinational logic synthesis based on the dual form of Reed-Muller representation.

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    In certain applications, AND/XOR (Reed-Muller), and ORlXNOR (Dualform of Reed-Muller) logic have shown some attractive advantages over thestandard Sum of Products (SOP) and Product of Sums (POS). Bidirectionalconversion algorithms between SOP and AND/XOR also between POS andORlXNOR based on Sparse and partitioning techniques are presented for multipleoutput Boolean functions. The developed programs are tested for somebenchmarks with up to 20 inputs and 40 outputs.A new direct method is presented to calculate the coefficients of the FixedPolarity Dual Reed-Muller (FPDRM) from the truth vector of the POS. AnyBoolean function can be expressed by FPDRM forms. There are 211 polarities foran n-variable function and the number of sum terms depends on these polarities.Finding the best polarity is costly interims of CPU time, in order to search for thebest polarity which will lead to the minimum number of sums for a particularfunction. Therefore, an algorithm is developed to compute all the coefficients ofthe Fixed Polarity Dual Reed-Muller (FPDRM) with polarity p from any polarity q.This technique is used to find the best polarity of FPDRM among the 211 fixedpolarities. The algorithm is based on the Dual- polarity property and the Gray codestrategy. Therefore, there is no need to start from POS form to find FPDRMcoefficients for all the polarities. The proposed methods are efficient in terms ofmemory size and CPU time. A fast algorithm is developed and implemented in Clanguage which can convert between POSs and FPDRMs. The program was testedfor up to 23 variables. A modified version of the same program was used to findthe best polarity. For up to 13 variables the CPU time was less than 42 seconds.To search for the optimal polarity for large number of variables and toreduce the se arch time 0 ffinding the 0 ptimal polarity 0 fthe function, two newalgorithms are developed and presented in this thesis. The first one is used toconvert between P OS and Positive Polarity Dual Reed-Muller (PPDRM) forms.The second algorithm will find the optimal fixed polarity for the FPDRM amongthe 211 different polarities for large n-variable functions. The most popularminimization criterion of the FPDRM form is obtained by the exhaustive search ofthe entire polarity vector. A non-exhaustive method for FPDRM expansions ispresented. The new algorithms are based on separation of the truth vector (T) ofPOSs around each variable Xi into two groups. Instead of generating all of thepolarity sets and searching for the best polarity, this algorithm will find the optimalpolarity using the separation and sparse techniques, which will lead to optimalpolarity. Time efficiency and computing speed are thus achieved in this technique.The algorithms don't require a large size of memory and don't require a long CPUtime. The two algorithms are implemented in C language and tested for somebenchmark. The proposed methods are fast and efficient as shown in theexperimental results and can be used for large number of variables

    Classification and properties of fast linearly independent logic transformations

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    Acta Cybernetica : Volume 14. Number 2.

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    A study of arithmetic circuits and the effect of utilising Reed-Muller techniques

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    Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that Reed-Muller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature.This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic.F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in Reed-Muller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions.The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work

    The 1st Conference of PhD Students in Computer Science

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