An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis

At sub-nanometre technology, temperature is one of the important design parameters to be taken care of during the target implementation for the circuit for its long term and reliable operation. High device package density leads to high power density that generates high temperatures. The temperature of a chip is directly proportional to the power density of the chip. So, the power density of a chip can be minimized to reduce the possibility of the high temperature generation. Temperature minimization approaches are generally addressed at the physical design level but it incurs high cooling cost. To reduce the cooling cost, the temperature minimization approaches can be addressed at the logic level. In this work, the Non-Dominated Sorting Genetic Algorithm-II (NSGA-II) based multi-objective heuristic approach is proposed to select the efficient input variable polarity of Mixed Polarity Reed-Muller (MPRM) expansion for simultaneous optimization of area, power, and temperature. A Pareto optimal solution set is obtained from the vast solution set of 3n (‘n’ is the number of input variables) different polarities of MPRM. Tabular technique is used for input polarity conversion from Sum-of-Product (SOP) form to MPRM form. Finally, using CADENCE and HotSpot tool absolute temperature, silicon area and power consumption of the synthesized circuits are calculated and are reported. The proposed algorithm saves around 76.20% silicon area, 29.09% power dissipation and reduces 17.06% peak temperature in comparison with the reported values in the literature

Canonical multi-valued input Reed-Muller trees and forms

There is recently an increased interest in logic synthesis using EXOR gates. The paper introduces the fundamental concept of Orthogonal Expansion, which generalizes the ring form of the Shannon expansion to the logic with multiple-valued (mv) inputs. Based on this concept we are able to define a family of canonical tree circuits. Such circuits can be considered for binary and multiple-valued input cases. They can be multi-level (trees and DAG's) or flattened to two-level AND-EXOR circuits. Input decoders similar to those used in Sum of Products (SOP) PLA's are used in realizations of multiple-valued input functions. In the case of the binary logic the family of flattened AND-EXOR circuits includes several forms discussed by Davio and Green. For the case of the logic with multiple-valued inputs, the family of the flattened mv AND-EXOR circuits includes three expansions known from literature and two new expansions

Combinational logic synthesis based on the dual form of Reed-Muller representation

In certain applications, AND/XOR (Reed-Muller), and ORlXNOR (Dual form of Reed-Muller) logic have shown some attractive advantages over the standard Sum of Products (SOP) and Product of Sums (POS). Bidirectional conversion algorithms between SOP and AND/XOR also between POS and ORlXNOR based on Sparse and partitioning techniques are presented for multiple output Boolean functions. The developed programs are tested for some benchmarks with up to 20 inputs and 40 outputs. A new direct method is presented to calculate the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) from the truth vector of the POS. Any Boolean function can be expressed by FPDRM forms. There are 211 polarities for an n-variable function and the number of sum terms depends on these polarities. Finding the best polarity is costly interims of CPU time, in order to search for the best polarity which will lead to the minimum number of sums for a particular function. Therefore, an algorithm is developed to compute all the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) with polarity p from any polarity q. This technique is used to find the best polarity of FPDRM among the 211 fixed polarities. The algorithm is based on the Dual- polarity property and the Gray code strategy. Therefore, there is no need to start from POS form to find FPDRM coefficients for all the polarities. The proposed methods are efficient in terms of memory size and CPU time. A fast algorithm is developed and implemented in C language which can convert between POSs and FPDRMs. The program was tested for up to 23 variables. A modified version of the same program was used to find the best polarity. For up to 13 variables the CPU time was less than 42 seconds. To search for the optimal polarity for large number of variables and to reduce the se arch time 0 ffinding the 0 ptimal polarity 0 fthe function, two new algorithms are developed and presented in this thesis. The first one is used to convert between P OS and Positive Polarity Dual Reed-Muller (PPDRM) forms. The second algorithm will find the optimal fixed polarity for the FPDRM among the 211 different polarities for large n-variable functions. The most popular minimization criterion of the FPDRM form is obtained by the exhaustive search of the entire polarity vector. A non-exhaustive method for FPDRM expansions is presented. The new algorithms are based on separation of the truth vector (T) of POSs around each variable Xi into two groups. Instead of generating all of the polarity sets and searching for the best polarity, this algorithm will find the optimal polarity using the separation and sparse techniques, which will lead to optimal polarity. Time efficiency and computing speed are thus achieved in this technique. The algorithms don't require a large size of memory and don't require a long CPU time. The two algorithms are implemented in C language and tested for some benchmark. The proposed methods are fast and efficient as shown in the experimental results and can be used for large number of variables.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Combinational logic synthesis based on the dual form of Reed-Muller representation.

In certain applications, AND/XOR (Reed-Muller), and ORlXNOR (Dualform of Reed-Muller) logic have shown some attractive advantages over thestandard Sum of Products (SOP) and Product of Sums (POS). Bidirectionalconversion algorithms between SOP and AND/XOR also between POS andORlXNOR based on Sparse and partitioning techniques are presented for multipleoutput Boolean functions. The developed programs are tested for somebenchmarks with up to 20 inputs and 40 outputs.A new direct method is presented to calculate the coefficients of the FixedPolarity Dual Reed-Muller (FPDRM) from the truth vector of the POS. AnyBoolean function can be expressed by FPDRM forms. There are 211 polarities foran n-variable function and the number of sum terms depends on these polarities.Finding the best polarity is costly interims of CPU time, in order to search for thebest polarity which will lead to the minimum number of sums for a particularfunction. Therefore, an algorithm is developed to compute all the coefficients ofthe Fixed Polarity Dual Reed-Muller (FPDRM) with polarity p from any polarity q.This technique is used to find the best polarity of FPDRM among the 211 fixedpolarities. The algorithm is based on the Dual- polarity property and the Gray codestrategy. Therefore, there is no need to start from POS form to find FPDRMcoefficients for all the polarities. The proposed methods are efficient in terms ofmemory size and CPU time. A fast algorithm is developed and implemented in Clanguage which can convert between POSs and FPDRMs. The program was testedfor up to 23 variables. A modified version of the same program was used to findthe best polarity. For up to 13 variables the CPU time was less than 42 seconds.To search for the optimal polarity for large number of variables and toreduce the se arch time 0 ffinding the 0 ptimal polarity 0 fthe function, two newalgorithms are developed and presented in this thesis. The first one is used toconvert between P OS and Positive Polarity Dual Reed-Muller (PPDRM) forms.The second algorithm will find the optimal fixed polarity for the FPDRM amongthe 211 different polarities for large n-variable functions. The most popularminimization criterion of the FPDRM form is obtained by the exhaustive search ofthe entire polarity vector. A non-exhaustive method for FPDRM expansions ispresented. The new algorithms are based on separation of the truth vector (T) ofPOSs around each variable Xi into two groups. Instead of generating all of thepolarity sets and searching for the best polarity, this algorithm will find the optimalpolarity using the separation and sparse techniques, which will lead to optimalpolarity. Time efficiency and computing speed are thus achieved in this technique.The algorithms don't require a large size of memory and don't require a long CPUtime. The two algorithms are implemented in C language and tested for somebenchmark. The proposed methods are fast and efficient as shown in theexperimental results and can be used for large number of variables

Automated synthesis and optimization of multilevel logic circuits.

With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synthesis plays an even more important role due to its flexibility and compactness.The history of symbolic logic and some typical techniques for multilevel logic synthesisare reviewed. These methods include algorithmic approach; Rule-Based approach; BinaryDecision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approachand several perturbation applications.One new kind of don't cares (DCs), called functional DCs has been proposed for multilevellogic synthesis. The conventional two-level cubes are generalized to multilevel cubes.Then functional DCs are generated based on the properties of containment. The conceptof containment is more general than unateness which leads to the generation of newDCs. A separate C program has been developed to utilize the functional DCs generatedas a Boolean function is decomposed for both single output and multiple output functions.The program can produce better results than script.rugged of SIS, developed by UC Berkeley,both in area and speed in less CPU time for a number of testcases from MCNC andIWLS'93 benchmarks.In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantagesover the standard Boolean logic based on AND JOR operations. A bidirectionalconversion algorithm between these two paradigms is presented based on the concept of polarityfor sum-of-products (SOP) Boolean functions, multiple segment and multiple pointerfacilities. Experimental results show that the algorithm is much faster than the previouslypublished programs for any fixed polarity. Based on this algorithm, a new technique calledredundancy-removal is applied to generalize the idea to very large multiple output Booleanfunctions. Results for benchmarks with up to 199 inputs and 99 outputs are presented.Applying the preceding conversion program, any Boolean functions can be expressedby fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function andthe number of product terms depends on these polarities. The problem of exact polarityminimization is computationally extensive and current programs are only suitable whenn :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logicand Reed-Muller logic, a fast algorithm is developed and implemented in C language whichcan find the best polarity for multiple output functions. Benchmark examples of up to 25inputs and 29 outputs run on a personal computer are given.After the best polarity for a Boolean function is calculated, this function can be furthersimplified using mixed polarity methods by combining the adjacent product terms. Hence,an efficient program is developed based on decomposition strategy to implement mixedpolarity minimization for both single output and very large multiple output Boolean functions.Experimental results show that the numbers of product terms are much less thanthe results produced by ESPRESSO for some categories of functions

On the descriptional complexity of iterative arrays

The descriptional complexity of iterative arrays (lAs) is studied. Iterative arrays are a parallel computational model with a sequential processing of the input. It is shown that lAs when compared to deterministic finite automata or pushdown automata may provide savings in size which are not bounded by any recursive function, so-called non-recursive trade-offs. Additional non-recursive trade-offs are proven to exist between lAs working in linear time and lAs working in real time. Furthermore, the descriptional complexity of lAs is compared with cellular automata (CAs) and non-recursive trade-offs are proven between two restricted classes. Finally, it is shown that many decidability questions for lAs are undecidable and not semidecidable