A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Switching Performance Evaluation, Design, and Test of a Robust 10 kV SiC MOSFET Based Phase Leg for Modular Medium Voltage Converters

10 kV SiC MOSFETs are one of the most promising power semiconductor devices for next-generation high-performance modular medium voltage (MV) converters. With extraordinary device characteristics, 10 kV SiC MOSFETs also bring a variety of challenges in the design and test of MV converters. To tackle these inherent challenges, this dissertation focuses on a robust half bridge (HB) phase leg based on 10 kV SiC MOSFETs for modular MV converters. A baseline design and test of the phase leg is established first as the foundation of the research in this dissertation. Thorough evaluation of 10 kV SiC MOSFETs’ switching performance in a phase leg is necessary before applying them in MV converters. The impact of parasitic capacitors and the freewheeling diode is investigated to understand the switching performance more extensively and guide the converter design. One non-negligible challenge is the flashover fault resulting from the premature insulation breakdown, a short circuit fault with extremely fast transients. A device model is established to analyze the behavior of 10 kV SiC MOSFETs when the fault occurs in a phase leg thoroughly. Subsequently, the gate driver and protection design considerations are summarized to achieve lower short circuit current and overvoltage and ensure the survival of the MOSFET that in ON state when the fault happens. Furthermore, it is challenging to design the overcurrent/short circuit protection with fast response and strong noise immunity under fast switching transients for 10 kV SiC MOSFETs. The noise immunity of the desaturation (desat) protection is studied quantitatively to provide design guidelines for noise immunity enhancement. Then, the protection scheme based on desat protection is developed and validated withimmunity, the strong noise immunity of the developed protection is also successfully validated. In addition, a simple test scheme is proposed and validated experimentally, in order to qualify the HB phase leg based on the 10 kV SiC MOSFET comprehensively for the modular MV converter applications. The test scheme includes the ac-dc continuous test with two phase legs in series to create the testing condition similar to what is generated in a modular MV converter, especially the high dv/dt. The test scheme can fully test the capability of the phase leg to withstand high dv/dt and its resulting noise

Hybrid behavioral-analytical loss model for a high frequency and low load DC/DC buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time (below 8.5 seconds) and a good accuracy, which makes this model suitable for the optimization process of the losses in the design of a converter. It has been validated by simulation and experimentally with one GaN power transistor and three Si MOSFETs. Results show good agreement between measurements and the mode

Loss model for a high frequency and low load DC/DC synchronous buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time and a good accuracy. It has been validated by simulation and experimentally with one Ga, power transistor and two Si MOSFETs. Results show good agreement between measurements and the model

Modeling, Measurement and Mitigation of Fast Switching Issues in Voltage Source Inverters

Wide-bandgap devices are enjoying wider adoption across the power electronics industry for their superior properties and the resulting opportunities for higher efficiency and power density. However, various issues arise due to the faster switching speed, including switching transient voltage overshoot, unstable oscillation, gate driving and evaluation difficulty, measurement and monitoring challenge, and potential load insulation degradation. This dissertation first sets out to model and understand the switching transient voltage overshoots. Unique oscillation patterns and features of the turn-on and turn-off overvoltage are discovered and analyzed, which provides new insights into the switching transient. During the experimental characterization, a new unstable oscillation pattern is found during the trench MOSFET\u27s turn-off transient. The MOSFET channel may be falsely turned back on, resulting in severe oscillation and possible loss of control. Time-domain and large-signal analytical models are established, which reveals the negative impact of common-source inductances and unconventional capacitance curve of trench MOSFET. Besides the devices themselves, another determining part in their switching transient behavior is the gate driver. A programmable gate driver platform is proposed to readily adapt to different power semiconductors and driving schemes, which can greatly facilitate the evaluation and comparison of different devices and driving schemes. The faster switching speed of wide-bandgap devices also requires more demanding measurement and monitoring solutions. A novel combinational Rogowski coil concept is proposed, which leverages the self-integrating feature to further increase the bandwidth. Prototypes achieved more than 300 MHz bandwidth, while keeping the cross-sectional area less than 2.5 mm$^2$. Finally, the very high voltage slew rate of wide-bandgap devices may negatively impact the motor load insulation. Attempting to fully utilize the higher switching frequency capability, sinewave and $dv/dt$ filters are compared. It is shown that sinewave filters can achieve higher efficiency and power density than $dv/dt$ filters, especially for high frequency applications