A Network Traffic Generator Model for Fast Network-on-Chip Simulation

For Systems-on-Chip (SoCs) development, a predomi-nant part of the design time is the simulation time. Perfor-mance evaluation and design space exploration of such sys-tems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast and effective Network-on-Chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an IP core in a reference environment, the TG can subsequently emulate the core’s communication behavior in different en-vironments. Access patterns and resource contention in a system are dependent on the interconnect architecture, and our TG is designed to capture the resulting reactiveness. The regenerated traffic, which represents a realistic work-load, can thus be used to undertake faster architectural ex-ploration of interconnection alternatives, effectively decou-pling simulation of IP cores and of interconnect fabrics. The results with the TG on an AMBA interconnect show a sim-ulation time speedup above a factor of 2 over a complete system simulation, with close to 100 % accuracy.

A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms

Optimal simulation speed and synthesizability are contradictory requirements for a hardware description language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed-point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them

Quantization effects in the polyphase N-path IIR structure

Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL

A Flexible Implementation of a Matrix Laurent Series-Based 16-Point Fast Fourier and Hartley Transforms

This paper describes a flexible architecture for implementing a new fast computation of the discrete Fourier and Hartley transforms, which is based on a matrix Laurent series. The device calculates the transforms based on a single bit selection operator. The hardware structure and synthesis are presented, which handled a 16-point fast transform in 65 nsec, with a Xilinx SPARTAN 3E device.Comment: 4 pages, 4 figures. IEEE VI Southern Programmable Logic Conference 201

Privacy Leakages in Approximate Adders

Approximate computing has recently emerged as a promising method to meet the low power requirements of digital designs. The erroneous outputs produced in approximate computing can be partially a function of each chip's process variation. We show that, in such schemes, the erroneous outputs produced on each chip instance can reveal the identity of the chip that performed the computation, possibly jeopardizing user privacy. In this work, we perform simulation experiments on 32-bit Ripple Carry Adders, Carry Lookahead Adders, and Han-Carlson Adders running at over-scaled operating points. Our results show that identification is possible, we contrast the identifiability of each type of adder, and we quantify how success of identification varies with the extent of over-scaling and noise. Our results are the first to show that approximate digital computations may compromise privacy. Designers of future approximate computing systems should be aware of the possible privacy leakages and decide whether mitigation is warranted in their application.Comment: 2017 IEEE International Symposium on Circuits and Systems (ISCAS