5,862 research outputs found

    Two computational primitives for algorithmic self-assembly: Copying and counting

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    Copying and counting are useful primitive operations for computation and construction. We have made DNA crystals that copy and crystals that count as they grow. For counting, 16 oligonucleotides assemble into four DNA Wang tiles that subsequently crystallize on a polymeric nucleating scaffold strand, arranging themselves in a binary counting pattern that could serve as a template for a molecular electronic demultiplexing circuit. Although the yield of counting crystals is low, and per-tile error rates in such crystals is roughly 10%, this work demonstrates the potential of algorithmic self-assembly to create complex nanoscale patterns of technological interest. A subset of the tiles for counting form information-bearing DNA tubes that copy bit strings from layer to layer along their length

    Pre-Matrix Balancing of Challenging Chemical Equations with a Simple Formula Register and Middle School Arithmetic

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    This paper describes a procedure employing basic relational concepts (analogous to certain matrix algebra concepts), but structured by a simple formula register and using only middle school arithmetic to balance chemical equations ranging from easy to moderate to difïŹcult redox reactions. This procedure allows average students and below average students to experience ready success in balancing, thus avoiding a traditional source of frustration and failure which might contribute to their losing interest in chemistry. One interesting serendipity of this procedure is how quickly it turns able pre-matrix students into extremely fast and accurate balaneers

    Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

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    Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
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