SCEE 2008 book of abstracts : the 7th International Conference on Scientific Computing in Electrical Engineering (SCEE 2008), September 28 – October 3, 2008, Helsinki University of Technology, Espoo, Finland

This report contains abstracts of presentations given at the SCEE 2008 conference.reviewe

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Efficient Interconnection Schemes for VLSI and Parallel Computation

This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson\u27s fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these universal networks can efficiently simulate competing networks by means of an appropriate correspondence between network components and efficient algorithms for routing messages on the universal network. In particular, a universal network of area A can simulate competing networks with O(lg^3A) slowdown (in bit-times), using a very simple randomized routing algorithm and simple network components. Alternatively, a packet routing scheme of Leighton, Maggs, and Rao can be used in conjunction with more sophisticated switching components to achieve O(lg^2 A) slowdown. Several other important aspects of universality are also discussed. It is shown that universal networks can be constructed in area linear in the number of processors, so that there is no need to restrict the density of processors in competing networks. Also results are presented for comparisons between networks of different size or with processors of different sizes (as determined by the amount of attached memory). Of particular interest is the fact that a universal network built from sufficiently small processors can simulate (with the slowdown already quoted) any competing network of comparable size regardless of the size of processors in the competing network. In addition, many of the results given do not require the usual assumption of unit wire delay. Finally, though most of the discussion is in the two-dimensional world, the results are shown to apply in three dimensions by way of a simple demonstration of general results on graph layout in three dimensions. The second main problem considered in this thesis is channel routing when many layers of interconnect are available, a scenario that is becoming more and more meaningful as chip fabrication technologies advance. This thesis describes a system MulCh for multilayer channel routing which extends the Chameleon system developed at U. C. Berkeley. Like Chameleon, MulCh divides a multilayer problem into essentially independent subproblems of at most three layers, but unlike Chameleon, MulCh considers the possibility of using partitions comprised of a single layer instead of only partitions of two or three layers. Experimental results show that MulCh often performs better than Chameleon in terms of channel width, total net length, and number of vias. In addition to a description of MulCh as implemented, this thesis provides improved algorithms for subtasks performed by MulCh, thereby indicating potential improvements in the speed and performance of multilayer channel routing. In particular, a linear time algorithm is given for determining the minimum width required for a single-layer channel routing problem, and an algorithm is given for maintaining the density of a collection of nets in logarithmic time per net insertion. The last part of this thesis shows that straightforward techniques for implementing finite-state machines are optimal in the worst case. Specifically, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires (ks lg s) area to lay out its realization. For nondeterministic machines, there is an analogous lower bound of (ks^2) area

Reduced-order modeling of power electronics components and systems

This dissertation addresses the seemingly inevitable compromise between modeling fidelity and simulation speed in power electronics. Higher-order effects are considered at the component and system levels. Order-reduction techniques are applied to provide insight into accurate, computationally efficient component-level (via reduced-order physics-based model) and system-level simulations (via multiresolution simulation). Proposed high-order models, verified with hardware measurements, are, in turn, used to verify the accuracy of final reduced-order models for both small- and large-signal excitations. At the component level, dynamic high-fidelity magnetic equivalent circuits are introduced for laminated and solid magnetic cores. Automated linear and nonlinear order-reduction techniques are introduced for linear magnetic systems, saturated systems, systems with relative motion, and multiple-winding systems, to extract the desired essential system dynamics. Finite-element models of magnetic components incorporating relative motion are set forth and then reduced. At the system level, a framework for multiresolution simulation of switching converters is developed. Multiresolution simulation provides an alternative method to analyze power converters by providing an appropriate amount of detail based on the time scale and phenomenon being considered. A detailed full-order converter model is built based upon high-order component models and accurate switching transitions. Efficient order-reduction techniques are used to extract several lower-order models for the desired resolution of the simulation. This simulation framework is extended to higher-order converters, converters with nonlinear elements, and closed-loop systems. The resulting rapid-to-integrate component models and flexible simulation frameworks could form the computational core of future virtual prototyping design and analysis environments for energy processing units

The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m^3 and is operated in a 0.5 T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb--Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report.Comment: 55 pages, 82 figure

Theoretical investigation of photon manipulation for quantum computing and quantum information processing

Quantum computing and quantum information processing are fast developing fields. As more and more qubits are integrated into the quantum computing systems, a deeper understanding and more careful modeling of the dynamics of these quantum systems in presence of driving and/or loss are necessary, not only for optimizing existing quantum devices, but also for designing and achieving novel method for more precise manipulation of these quantum systems. Our work investigating these quantum systems is inspired by quantum optics, a field focused on the quantum description of light and light-matter interactions. In this thesis, we use the theoretical toolboxes provided by quantum optics as well as condensed matter theory to investigate and model realistic quantum systems. Specifically, we focus on the Nitrogen-vacancy centers in diamond crystal, a Josephson parametric amplifier (that uses Josephson junctions as its non-linear elements), and plasmonic nanowire system. With the knowledge of the dynamics of these systems, we proposed single-photon heralded two-NV center quantum gates; designed and optimized the superconducting circuit for a Josephson parametric amplifier to improve the amplifier's saturation power; and designed new methods for robust light manipulation using topologically protected plasmonic modes. All the devices that we study are either ready to be implemented in experiments or have already been built. Further, as discussed in this thesis, our theoretical analysis of NV-centers can be extended to similar device types like solid-state defect centers, while our analysis of Josephson parametric amplifiers can be extended to other types of superconducting circuit systems

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices