A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

A Low Speed BIST Framework for High Speed Circuit Testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Étude de faisabilité d'une méthodologie de test exploitant le test par le courant IDDQ, et l'intéraction d'autres méthodes de test de diagnostic

Cette thèse porte globalement sur l'élaboration d'une méthodologie permettant d'améliorer le test des circuits intégrés (CI), et ce, en utilisant des concepts propres au diagnostic et en se basant sur l'interacfion des méthodes de test existantes. Le premier objectif de cette thèse est la généralisation plus poussée de la méthode de diagnostic basée sur les signatures probabilistes du courant AIDDQ, et ce, à plusieurs niveaux. D'une part, nous avons développé plusieurs modèles de pannes de courts-circuits incluant la totalité des types de portes logiques de la technologie CMOS 0.35|xm. D'autre part, nous avons amélioré la technique de réduction des sites physiques de courts-circuits; nous parlons de celle basée sur les résultats des sorties erronées du circuit sous test obtenus à l'aide de son émulation (ou son test). Cette technique supportait des circuits purement combinatoires. L'améliorafion apportée permet maintenant d'ufiliser cette technique sur des circuits séquentiels. Nous avons également présenté les derniers résultats de réduction des sites de court-circuit, et ce. en se basant sur les signatures AIDDQ, les capacités parasites de routage extraites du dessin des masques et les erreurs logiques observées à la sortie du circuit, et ce, pour les technologies 0.35|a.m et 90nm. La combinaison de ces trois techniques réduit significativement le nombre de sites de courts-circuits à considérer dans le diagnostic. Les résultats de simulation confirment que le nombre de sites de court-circuit est réduit de O(N') à 0(N), où N est le nombre de noeuds dans le circuit. Du coté de l'outil logiciel permettant l'émulation de la méthode de diagnostic proposée, nous avons complété sa conception, et nous avons défini les conditions permettant son utilisation dans un environnement de test en temps réel. Le deuxième objectif de cette thèse est l'introduction d'une nouvelle stratégie d'optimisation pour le test adaptatif de haute qualité. La stratégie proposée permet dans un premier temps de couvrir les pannes qui habituellement ne causent pas une consommation anormale du courant IDDQ avec le minimum de vecteurs possibles qui sont appliqués à tous les circuits; et dans un deuxième temps, propose deux pistes de traitement pour les pannes qui habituellement causent une élévation du courant IDDQ- Le traitement a priori (prévision) est basé sur l'ajout d'autres vecteurs de test pour couvrir les sites non couverts par les tests logiques ou de délais. Le traitement a posteriori (guérison) est basé sur un diagnostic rapide sur les sites non couverts. Nous faisons appel à la méthode de diagnostic proposée avec quelques modifications. Ce traitement correspond à une stratégie d'optimisation visant à n'appliquer les vecteurs supplémentaires que sur les CI montrant des symptômes particuliers

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

Fault simulation and test generation for small delay faults

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which models delay faults caused by the combination of spot defects and parametric process variation. According to the new model, a realistic delay fault coverage metric has been developed. Traditional path delay fault coverage metrics result in unrealistically low fault coverage, and the real test quality is not reflected. The new metric uses a statistical approach and the simulation based fault coverage is consistent with silicon data. Fast simulation algorithms are also included in this dissertation. The new metric suggests that testing the K longest paths per gate (KLPG) has high detection probability for small delay faults under process variation. In this dissertation, a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate for both combinational and sequential circuits is presented. Many techniques are used to reduce search space and CPU time significantly. Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288. The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Scanning near-field photon emission microscopy

Ph.DDOCTOR OF PHILOSOPH