A novel entropy production based full-chip TSV fatigue analysis

Through-silicon vias (TSVs) are subject to thermal fatigue due to stress over time, no matter how small the stress is. Existing works on TSV fatigue all rely on measurement-based parameters to estimate the lifetime, and cannot consider detailed thermal profiles. In this paper, we propose a new method for TSV fatigue prediction using entropy production during thermal cycles. By combining thermodynamics and mechanics laws, the fatigue process can be quantitatively evaluated with detailed thermal profiles. Experimental results show that interestingly, the landing pad possesses the most easy-to-fail region, which generates up to 50% more entropy compared with the TSV body. The impact of landing pad dimension and TSV geometries are also studied, providing guidance for reliability enhancement. Finally, full-chip fatigue analysis is performed based on stress superposition. To the best of the authors\u27 knowledge, this is the first TSV fatigue model that is free of measurement data fitting, the first that is capable of considering detailed thermal profiles, and the first framework for efficient full-chip TSV fatigue analysis. --Abstract, page iii

Glass multilayer bonding for high density interconnect substrates

The aim of this research was the investigation of bonding borosilicate glass sheets, its trade mark CMZ, 100μm thickness, to create multilayer substrates capable of supporting high-density electrical interconnections. CMZ glass was chosen as it has a coefficient of thermal expansion that is close to that of silicon, thereby minimising thermal stresses in assemblies generated by manufacturing processes or service conditions. Two different methods of bonding the glass were used in this study; pressure assisted low temperature bonding (PALTB), and water glass bonding, using Sodium Trisilicate (Na2Si3O7) solution. These two bonding methods have already been applied in electronics manufacturing applications, such as silicon wafer bonding and multichip modules (MCMs). However, glass-to-glass bonding is a relatively new subject and this study is an attempt to standardise bonding processes. Additionally, the concept of using glass as a multilayer substrate provides a foundation for further exploration by other investigators. Initial tests that were carried out before standardising the procedures for these two methods showed that a two-stage bonding process provided optimum results. A preliminary stage commenced by placing the cleaned (using Decon 90 solution) samples in a vacuum oven for 15 minutes, then heating at 100oC for 1hr. The permanent stage was then achieved by heating the samples in a conventional oven at temperatures from 200 to 400oC, for different periods. At this stage, the main difference between the two methods was the application of pressure (1-2MPa) during heating of the PALTB samples. To evaluate the quality of the bonds, qualitative tests such as visual, optical microscope and dye penetrant were used. In addition, to estimate the strength and the rigidity of the interlayer bonds, two quantitative tests, comprising of deflection under cyclic stresses and crack opening were used. Thermal cycling and humidity tests were also used to assess resistance of the bonds to environmental effects. The results showed that heating to 100oC was insufficient to enhance the bonds, as occasionally a sudden increase of deflection was observed indicating slippage/delamination. These bonds were enhanced during the permanent bonding stage by heating to 300oC in PALTB, under a pressure of 1-2MPa. The crack-opening test showed that the delamination distances of the bonds in the permanent stage were lower than that for preliminary bonding in both bonding methods. The delamination distances from the crack opening tests were used to calculate the strain energy release rate (GIC) and fracture toughness (KIC) values of the interlayers. The results showed that the KIC values of the permanent PALTB and water glass interlayers were higher than 1MPa.m0.5, while the KIC value of the CMZ glass, determined by linear elastic fracture mechanics, was around 0.8MPa.m0.5. The optical observations revealed that the prepared bonded sheets did not delaminate or break after thermal cycling and humidity tests

Effects of underfill material on solder deformation and damage in 3D packages

This paper will examine the effects of the introduction of a periodic boundary condition and the presence of underfill material on the stress and strain fields and evolution of failure of an FEA model that is representative of a solder joint in a 3D IC package. The model solder joint is placed between two silicon substrates in contact with through-silicon vias without any other devices or components attached. Differing solder joint thicknesses, both with and without underfill, will be examined to study the effect on the stress and strain fields as well as the evolution of failure in the solder joint. A dynamic loading on the FEA model will be used to examine the fracture pattern and mode of failure when the solder thickness is varied both with and without underfill material present

Cost effective high efficiency solar cells

textTo make solar energy mainstream, lower-cost and more efficient power generation is key. A lot of effort in the silicon photovoltaic industry has gone into using fewer raw materials (i.e., silicon) and using more inexpensive processing techniques and materials to reduce cost. Utilizing thinner substrates not only reduces cost, but improves cell efficiency provided both front and back surfaces are well-passivated. In the current work, a kerf-less process is developed in which ultra-thin (~25 [mu]m), flexible mono-crystalline silicon substrates can be obtained through an exfoliation technique from a thicker parent wafer. These substrates, when exfoliated, have thick metal backing which provides mechanical support to the thin silicon and enables ease of processing of the substrates for device fabrication. Optical, electrical, and reliability characterization studies for completed cells show this technology’s compatibility with a heterojunction solar cell process flow. Building on the promising results achieved on exfoliated substrates, further optimization work was carried out. Namely, an improved cleaning process was developed to remove front surface contamination on textured surfaces of exfoliated, flexible mono-crystalline silicon. This process is very effective at cleaning metallic and organic residues, without introducing additional contamination or degrading the supporting back metal used for ultra-thin substrate handling. Spectroscopic studies were performed to qualitatively and quantitatively understand the efficacy of different cleaning procedures in order to develop the new cleaning process. Results of the spectroscopic studies were further supported by comparing the electrical performance of cells fabricated with different cleans. To replace silver as contact metal with a cheaper substitute like nickel or copper, patterning and etching processes are generally used. A low-cost alternative is proposed, where a reusable shadow mask with a metal grid pattern is kept in contact with the surface of the substrate in a plasma-enhanced chemical vapor deposition chamber during silicon nitride deposition. This leaves a patterned silicon surface for selective metal growth by direct electro-deposition. The viability of this process flow is demonstrated by fabricating diffused junction n[superscript+]pp[superscript+] monofacial and bifacial cells and electrically characterizing them. Investigation of the factors limiting the efficiency of the cells was carried out by lifetime measurement experiments.Electrical and Computer Engineerin

Enhanced electrodeposition for the filling of micro-vias

This thesis investigated the introduction of megasound (MS) (1MHz) acoustic technology as an enhanced agitation method of an electrolyte solution for the electrochemical deposition of copper (Cu), used in electroplating processes. The thesis, carried out at Merlin Circuit Technology Ltd, studied the possibility of improving processing capabilities for use in Printed Circuit Board (PCB) industrial manufacture. Prior laboratory experiments demonstrated increased metallisation of vertical interconnect access (via) features in a Printed Circuit Board (PCB), which, if applied within manufacturing, would enable increased connectivity throughout a PCB and result in cost savings. PCB manufacturing quality after MS-assisted Cu electroplating was assessed by measurements of the topography of the electrodeposits, using scanning electron microscopy and white-light interferometry. Cu plating rate changes were also measured on the surface of the PCB and inside the vias. After plating Cu with MS-assistance, the macro and microscale surface composition was demonstrated to alter due to the direct influence of the acoustic waves. Systematic characteristic of the surface was conducted by varying the settings of the acoustic transducer device as well as the process parameters including electrical current distribution, bath additive chemistry and solution temperature. MS processing was shown to produce unique Cu artefacts. Their deleterious formation was demonstrated to be influenced by acoustic standing waves and microbubble formations at the electrolyte solution/PCB interface. Causes of these artefacts, microfluidic streaming and cavitation, were also observed and controlled to reduce the creation of these artefacts. MS plating Cu down through-hole via (THV) and blind-via (BV) interconnects was shown to produce measureable benefits. These include, for THVs, a 700 % increase of Cu plating deposit thickness within a 175 μm diameter, depth-to-width aspect ratio (ar) of 5.7:1, compared with processing under no-agitation conditions. For BVs, a 60 % average increase in Cu deposition in 150 μm and 200 μm, ar 1:1, was demonstrated against plating under standard manufacturing conditions - bubble agitation and panel movement.Engineering and Physical Research Council (EPSRC) grant number EP/G037523/

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-Force magnetometers

Tesi en modalitat de compendi de publicacionsToday, the most common form of mass-production semiconductor device fabrication is Complementary Metal-Oxide Semiconductor (CMOS) technology. The dedicated Integrated Circuit (IC) interfaces of commercial sensors are manufactured using this technology. The sensing elements are generally implemented using Micro-Electro-Mechanical-Systems (MEMS), which need to be manufactured using specialized micro-machining processes. Finally, the CMOS circuitry and the MEMS should ideally be combined in a single package. For some applications, integration of CMOS electronics and MEMS devices on a single chip (CMOS-MEMS) has the potential of reducing fabrication costs, size, parasitics and power consumption, compared to other integration approaches. Remarkably, a CMOS-MEMS device may be built with the back-end-of-line (BEOL) layers of the CMOS process. But, despite its advantages, this particular approach has proven to be very challenging given the current lack of commercial products in the market. The main objective of this Thesis is to prove that a high-performance MEMS, sealed and packaged in a standard package, may be accurately modeled and manufactured using the BEOL layers of a CMOS process in a reliable way. To attain this, the first highly reliable novel CMOS-MEMS Lorentz Force Magnetometer (LFM) was successfully designed, modeled, manufactured, characterized and subjected to several reliability tests, obtaining a comparable or superior performance to the typical solid-state magnetometers used in current smartphones. A novel technique to avoid magnetic offsets, the main drawback of LFMs, was presented and its performance confirmed experimentally. Initially, the issues encountered in the manufacturing process of MEMS using the BEOL layers of the CMOS process were discouraging. Vapor HF release of MEMS structures using the BEOL of CMOS wafers resulted in undesirable damaging effects that may lead to the conclusion that this manufacturing approach is not feasible. However, design techniques and workarounds for dealing with the observed issues were devised, tested and implemented in the design of the LFM presented in this Thesis, showing a clear path to successfully fabricate different MEMS devices using the BEOL.Hoy en día, la forma más común de producción en masa es una tecnología llamada Complementary Metal-Oxide Semiconductor (CMOS). La interfaz de los circuitos integrados (IC) de sensores comerciales se fabrica usando, precisamente, esta tecnología. Actualmente es común que los sensores se implementen usando Sistemas Micro-Electro-Mecánicos (MEMS), que necesitan ser fabricados usando procesos especiales de micro-mecanizado. En un último paso, la circuitería CMOS y el MEMS se combinan en un único elemento, llamado package. En algunas aplicaciones, la integración de la electrónica CMOS y los dispositivos MEMS en un único chip (CMOS-MEMS) alberga el potencial de reducir los costes de fabricación, el tamaño, los parásitos y el consumo, al compararla con otras formas de integración. Resulta notable que un dispositivo CMOS-MEMS pueda ser construido con las capas del back-end-of-line (BEOL) de un proceso CMOS. Pero, a pesar de sus ventajas, este enfoque ha demostrado ser un gran desafío como demuestra la falta de productos comerciales en el mercado. El objetivo principal de esta Tesis es probar que un MEMS de altas prestaciones, sellado y empaquetado en un encapsulado estándar, puede ser correctamente modelado y fabricado de una manera fiable usando las capas del BEOL de un proceso CMOS. Para probar esto mismo, el primer magnetómetro CMOS-MEMS de fuerza de Lorentz (LFM) fue exitosamente diseñado, modelado, fabricado, caracterizado y sometido a varias pruebas de fiabilidad, obteniendo un rendimiento comparable o superior al de los típicos magnetómetros de estado sólido, los cuales son usados en móviles actuales. Cabe destacar que en esta Tesis se presenta una novedosa técnica con la que se evitan offsets magnéticos, el mayor inconveniente de los magnetómetros de fuerza Lorentz. Su efectividad fue confirmada experimentalmente. En los inicios, los problemas asociados al proceso de fabricación de MEMS usando las capas BEOL de obleas CMOS resultaba desalentador. Liberar estructuras MEMS hechas con obleas CMOS con vapor de HF producía efectos no deseados que bien podrían llevar a la conclusión de que este enfoque de fabricación no es viable. Sin embargo, se idearon y probaron técnicas de diseño especiales y soluciones ad-hoc para contrarrestar estos efectos no deseados. Se implementaron en el diseño del magnetómetro de Lorentz presentado en esta Tesis, arrojando excelentes resultados, lo cual despeja el camino hacia la fabricación de diferentes dispositivos MEMS usando las capas BEOL.Postprint (published version

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Thermomechanical and mechanical characterization of a 3-axial MEMS gyroscope

Työn tavoitteena oli automaattisten, tehokkaiden ja edullisten testauslaitteistojen ja -menetelmien kehittäminen kolmiakselisten mikroelektromekaanisten (MEMS) gyroskooppien mekaaniseen ja termomekaaniseen karakterisointiin. Työn painotuksena oli testausmenetelmien ja -laitteistojen kehittäminen ja gyroskooppien vaurioanalyysit jäävät tämän työn ulkopuolelle. Gyroskooppi on kulmanopeuden mittaamiseen ja asennon aistimiseen käytettävä anturi. Mekaaninen karakteristointi kattaa gyroskooppien korkean G-arvon iskumaiset kuormitukset ja tärinäkuormitukset. Lämpömekaaninen karakterisointi kattaa gyroskooppien ympäristöolojen kontrolloimista lämpö-, kosteus- tai monikaasu -kaapissa. Tässä työssä kehitettiin menetelmä kolmiakselisten MEMS-gyroskooppien karakterisointiin lämpö- ja kosteuskaapissa. Menetelmä koostuu yksiakselisesta servomoottorista, servo-ohjaimesta ja ohjaussovelluksesta, jonka avulla voidaan samanaikaisesti mitata ja tallentaa gyroskooppien kulmanopeus kaikilta kolmelta (X, Y ja Z) akselilta sekä mitata ympäristön lämpötilaa. Korkean G-arvon iskumaisiin kuormituksiin tarkoitettu laitteisto koostuu pneumaattisesta iskutestauslaitteesta, jossa käytetään mekaanista iskua korkean G-arvon saavuttamiseen. Olemassa olevaa laitteistoa muutettiin siten että sillä voidaan saavuttaa suurempia G-arvoja (aina 80 000G:hen asti) ja mahdollistaa gyroskooppien tutkiminen eri asennoissa. Tärinäkuormituslaittesto koostuu signaaligeneraattorista ja täristinmoottorista, joka soveltuu gyroskooppien tärinätestaukseen. Signaaligeneraattoria käytetään eri taajuisten signaalimuotojen syöttämiseen täristinmoottorille, joka tärisee annetun syötteen mukaisesti. Pyörityslaitteen toiminnallisuutta testattiin yhdellä gyroskoopilla huoneenlämmössä. Gyroskoopin X, Y ja Z-akselien kulmanopeuksien keskiarvot sekä -hajonta mitattiin. Korkean g-arvon iskutestauslaitteistoa testattiin kuudella mittauksella, jossa gyroskoopit rikkoutuivat ensimmäisellä iskulla. Tärinätestauslaitteistoa testattiin yhdellä gyroskooppi-piirilevyllä. Gyroskooppi-piirilevyn päälle asetettiin kiihtyvyysanturi, jolla mitattiin tärinästä aiheutuvan kiihtyvyyden RMS-arvo, huippuarvo ja kokonaisenergia. Tulevat jatkotutkimukset keskittyvät pyöritys-, isku- ja tärinälaitteistoilla testattujen MEMS-gyroskooppien vaurioanalyysiin.The purpose of this thesis was to develop automated, efficient and economical methods for the mechanical and thermomechanical characterization of a digital 3-axial microelectromechanical systems (MEMS) gyroscope. The development of the test equipment and methods was the emphasis of this thesis, but the failure analyses of MEMS gyroscopes are beyond the scope of this work. A gyroscope is a device for measuring angular velocity and sensing change in orientation around its X, Y and Z-axis. The experimental part is divided into two sections, of which the first one is focused on high-G shock impact and vibration loading and the second on thermomechanical characterization. A rotation device was developed for the characterization of the MEMS gyroscopes in a temperature and humidity chamber. The rotation device consists of a oneaxial servo-motor, a servo-drive and a control program for the readout of angular velocity. The device is capable of simultaneously recording the angular velocities of the gyroscopes from all three axes while rotating the gyroscopes around a single axis. The device also records the temperature of the environment. The high-G shock impact equipment consists of a pneumatically assisted shock tester that relies on mechanical impact to generate the high-G shock pulse. An existing mechanical shock impact system was modified to gain higher G-values (up to 80 000G) and to enable the inspection of gyroscopes in different orientations. The vibration test equipment consists of a waveform generator and a vibration shaker, for the vibration testing of gyroscopes. The waveform generator is capable of outputting different waveforms with different frequencies to the shaker that vibrates with the given output. The functionality of the rotation device was tested with rotating one gyroscope board at room temperature. Respective averages and standard deviations of angular velocities were measured in the direction of X, Y and Z axes. The functionality of the high-G shock impact test equipment was verified with six measurements where all of the gyroscopes failed on first impact. The vibration test equipment was tested with one gyroscope board. Root mean square (RMS), peak value and total energy of acceleration were measured with an accelerometer placed on top of the vibrating gyroscope board

Emergency delivery of Vasopressin from an implantable MEMS rapid drug delivery device

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references.An implantable rapid drug delivery device based on micro-electro-mechanical systems (MEMS) technology was designed, fabricated and validated for the in vivo rapid delivery of vasopressin in a rabbit model. In vitro characterization of device performance found the device capable of reliably and reproducibly delivering 85% of its loaded drug solution. A comparison of intraperitoneal and subcutaneous injections of vasopressin in rabbits was performed to determine the implantation location for the device. Both routes of delivery were found to be viable implantation locations, and the less invasive subcutaneous site was chosen. Vasopressin was released from the subcutaneously implanted device in anesthetized rabbits and found to exert a measurable effect on blood pressure. The bioavailability of vasopressin delivered from the device was found to be 6.2% after one hour. Proof-of-concept experiments were also conducted to address long-term stability of drugs in the implanted device and wireless activation of the device. These experiments defined areas of future research for improvement of the device.by Hong Linh Ho Duc.Ph.D