Signal Processing for Caching Networks and Non-volatile Memories

The recent information explosion has created a pressing need for faster and more reliable data storage and transmission schemes. This thesis focuses on two systems: caching networks and non-volatile storage systems. It proposes network protocols to improve the efficiency of information delivery and signal processing schemes to reduce errors at the physical layer as well. This thesis first investigates caching and delivery strategies for content delivery networks. Caching has been investigated as a useful technique to reduce the network burden by prefetching some contents during o˙-peak hours. Coded caching [1] proposed by Maddah-Ali and Niesen is the foundation of our algorithms and it has been shown to be a useful technique which can reduce peak traffic rates by encoding transmissions so that different users can extract different information from the same packet. Content delivery networks store information distributed across multiple servers, so as to balance the load and avoid unrecoverable losses in case of node or disk failures. On one hand, distributed storage limits the capability of combining content from different servers into a single message, causing performance losses in coded caching schemes. But, on the other hand, the inherent redundancy existing in distributed storage systems can be used to improve the performance of those schemes through parallelism. This thesis proposes a scheme combining distributed storage of the content in multiple servers and an efficient coded caching algorithm for delivery to the users. This scheme is shown to reduce the peak transmission rate below that of state-of-the-art algorithms

Scaling and Resilience in Numerical Algorithms for Exascale Computing

The first Petascale supercomputer, the IBM Roadrunner, went online in 2008. Ten years later, the community is now looking ahead to a new generation of Exascale machines. During the decade that has passed, several hundred Petascale capable machines have been installed worldwide, yet despite the abundance of machines, applications that scale to their full size remain rare. Large clusters now routinely have 50.000+ cores, some have several million. This extreme level of parallelism, that has allowed a theoretical compute capacity in excess of a million billion operations per second, turns out to be difficult to use in many applications of practical interest. Processors often end up spending more time waiting for synchronization, communication, and other coordinating operations to complete, rather than actually computing. Component reliability is another challenge facing HPC developers. If even a single processor fail, among many thousands, the user is forced to restart traditional applications, wasting valuable compute time. These issues collectively manifest themselves as low parallel efficiency, resulting in waste of energy and computational resources. Future performance improvements are expected to continue to come in large part due to increased parallelism. One may therefore speculate that the difficulties currently faced, when scaling applications to Petascale machines, will progressively worsen, making it difficult for scientists to harness the full potential of Exascale computing. The thesis comprises two parts. Each part consists of several chapters discussing modifications of numerical algorithms to make them better suited for future Exascale machines. In the first part, the use of Parareal for Parallel-in-Time integration techniques for scalable numerical solution of partial differential equations is considered. We propose a new adaptive scheduler that optimize the parallel efficiency by minimizing the time-subdomain length without making communication of time-subdomains too costly. In conjunction with an appropriate preconditioner, we demonstrate that it is possible to obtain time-parallel speedup on the nonlinear shallow water equation, beyond what is possible using conventional spatial domain-decomposition techniques alone. The part is concluded with the proposal of a new method for constructing Parallel-in-Time integration schemes better suited for convection dominated problems. In the second part, new ways of mitigating the impact of hardware failures are developed and presented. The topic is introduced with the creation of a new fault-tolerant variant of Parareal. In the chapter that follows, a C++ Library for multi-level checkpointing is presented. The library uses lightweight in-memory checkpoints, protected trough the use of erasure codes, to mitigate the impact of failures by decreasing the overhead of checkpointing and minimizing the compute work lost. Erasure codes have the unfortunate property that if more data blocks are lost than parity codes created, the data is effectively considered unrecoverable. The final chapter contains a preliminary study on partial information recovery for incomplete checksums. Under the assumption that some meta knowledge exists on the structure of the data encoded, we show that the data lost may be recovered, at least partially. This result is of interest not only in HPC but also in data centers where erasure codes are widely used to protect data efficiently

Space station data system analysis/architecture study. Task 2: Options development DR-5. Volume 1: Technology options

The second task in the Space Station Data System (SSDS) Analysis/Architecture Study is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This volume identifies the preferred options in the technology category and characterizes these options with respect to performance attributes, constraints, cost, and risk. The technology category includes advanced materials, processes, and techniques that can be used to enhance the implementation of SSDS design structures. The specific areas discussed are mass storage, including space and round on-line storage and off-line storage; man/machine interface; data processing hardware, including flight computers and advanced/fault tolerant computer architectures; and software, including data compression algorithms, on-board high level languages, and software tools. Also discussed are artificial intelligence applications and hard-wire communications

Efficient and Effective Schemes for Streaming Media Delivery

The rapid expansion of the Internet and the increasingly wide deployment of wireless networks provide opportunities to deliver streaming media content to users at anywhere, anytime. To ensure good user experience, it is important to battle adversary effects, such as delay, loss and jitter. In this thesis, we first study efficient loss recovery schemes, which require pure XOR operations. In particular, we propose a novel scheme capable of recovering up to 3 packet losses, and it has the lowest complexity among all known schemes. We also propose an efficient algorithm for array codes decoding, which achieves significant throughput gain and energy savings over conventional codes. We believe these schemes are applicable to streaming applications, especially in wireless environments. We then study quality adaptation schemes for client buffer management. Our control-theoretic approach results in an efficient online rate control algorithm with analytically tractable performance. Extensive experimental results show that three goals are achieved: fast startup, continuous playback in the face of severe congestion, and maximal quality and smoothness over the entire streaming session. The scheme is later extended to streaming with limited quality levels, which is then directly applicable to existing systems

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi

NASA Tech Briefs, May 2011

Topics covered include: 1) Method to Estimate the Dissolved Air Content in Hydraulic Fluid; 2) Method for Measuring Collimator-Pointing Sensitivity to Temperature Changes; 3) High-Temperature Thermometer Using Cr-Doped GdAlO3 Broadband Luminescence; 4)Metrology Arrangement for Measuring the Positions of Mirrors of a Submillimeter Telescope; 5) On-Wafer S-Parameter Measurements in the 325-508-GHz Band; 6) Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications; 7) High-Speed Isolation Board for Flight Hardware Testing; 8) High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors; 9) 3D Orbit Visualization for Earth-Observing Missions; 10) MaROS: Web Visualization of Mars Orbiting and Landed Assets; 11) RAPID: Collaborative Commanding and Monitoring of Lunar Assets; 12) Image Segmentation, Registration, Compression, and Matching; 13) Image Calibration; 14) Rapid ISS Power Availability Simulator; 15) A Method of Strengthening Composite/Metal Joints; 16) Pre-Finishing of SiC for Optical Applications; 17) Optimization of Indium Bump Morphology for Improved Flip Chip Devices; 18) Measuring Moisture Levels in Graphite Epoxy Composite Sandwich Structures; 19) Marshall Convergent Spray Formulation Improvement for High Temperatures; 20) Real-Time Deposition Monitor for Ultrathin Conductive Films; 21) Optimized Li-Ion Electrolytes Containing Triphenyl Phosphate as a Flame-Retardant Additive; 22) Radiation-Resistant Hybrid Lotus Effect for Achieving Photoelectrocatalytic Self-Cleaning Anticontamination Coatings; 23) Improved, Low-Stress Economical Submerged Pipeline; 24) Optical Fiber Array Assemblies for Space Flight on the Lunar Reconnaissance Orbiter; 25) Local Leak Detection and Health Monitoring of Pressurized Tanks; 26) Dielectric Covered Planar Antennas at Submillimeter Wavelengths for Terahertz Imaging; 27) Automated Cryocooler Monitor and Control System; 28) Broadband Achromatic Phase Shifter for a Nulling Interferometer; 29) Super Dwarf Wheat for Growth in Confined Spaces; 30) Fine Guidance Sensing for Coronagraphic Observatories; 31) Single-Antenna Temperature- and Humidity-Sounding Microwave Receiver; 32) Multi-Wavelength, Multi-Beam, and Polarization-Sensitive Laser Transmitter for Surface Mapping; 33) Optical Communications Link to Airborne Transceiver; 34) Ascent Heating Thermal Analysis on Spacecraft Adaptor Fairings; 35) Entanglement in Self-Supervised Dynamics; 36) Prioritized LT Codes; 37) Fast Image Texture Classification Using Decision Trees; 38) Constraint Embedding Technique for Multibody System Dynamics; 39) Improved Systematic Pointing Error Model for the DSN Antennas; 40) Observability and Estimation of Distributed Space Systems via Local Information-Exchange Networks; 41) More-Accurate Model of Flows in Rocket Injectors; 42) In-Orbit Instrument-Pointing Calibration Using the Moon as a Target; 43) Reliability of Ceramic Column Grid Array Interconnect Packages Under Extreme Temperatures; 44) Six Degrees-of-Freedom Ascent Control for Small-Body Touch and Go; and 45) Optical-Path-Difference Linear Mechanism for the Panchromatic Fourier Transform Spectrometer

The future of space imaging. Report of a community-based study of an advanced camera for the Hubble Space Telescope

The scientific and technical basis for an Advanced Camera (AC) for the Hubble Space Telescope (HST) is discussed. In March 1992, the NASA Program Scientist for HST invited the Space Telescope Science Institute to conduct a community-based study of an AC, which would be installed on a scheduled HST servicing mission in 1999. The study had three phases: a broad community survey of views on candidate science program and required performance of the AC, an analysis of technical issues relating to its implementation, and a panel of experts to formulate conclusions and prioritize recommendations. From the assessment of the imaging tasks astronomers have proposed for or desired from HST, we believe the most valuable 1999 instrument would be a camera with both near ultraviolet/optical (NUVO) and far ultraviolet (FUV) sensitivity, and with both wide field and high resolution options

Architectural Techniques to Enable Reliable and Scalable Memory Systems

High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is seen as the key impediment towards using high-density devices, adopting new technologies, and even building the next Exascale supercomputer. To ensure even a bare-minimum level of reliability, present-day solutions tend to have high performance, power and area overheads. Ideally, we would like memory systems to remain robust, scalable, and implementable while keeping the overheads to a minimum. This dissertation describes how simple cross-layer architectural techniques can provide orders of magnitude higher reliability and enable seamless scalability for memory systems while incurring negligible overheads.Comment: PhD thesis, Georgia Institute of Technology (May 2017