A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

Mengenal pasti tahap pengetahuan pelajar tahun akhir Ijazah Sarjana Muda Kejuruteraan di KUiTTHO dalam bidang keusahawanan dari aspek pengurusan modal

Malaysia ialah sebuah negara membangun di dunia. Dalam proses pembangunan ini, hasrat negara untuk melahirkan bakal usahawan beijaya tidak boleh dipandang ringan. Oleh itu, pengetahuan dalam bidang keusahawanan perlu diberi perhatian dengan sewajarnya; antara aspek utama dalam keusahawanan ialah modal. Pengurusan modal yang tidak cekap menjadi punca utama kegagalan usahawan. Menyedari hakikat ini, kajian berkaitan Pengurusan Modal dijalankan ke atas 100 orang pelajar Tahun Akhir Kejuruteraan di KUiTTHO. Sampel ini dipilih kerana pelajar-pelajar ini akan menempuhi alam pekeijaan di mana mereka boleh memilih keusahawanan sebagai satu keijaya. Walau pun mereka bukanlah pelajar dari jurusan perniagaan, namun mereka mempunyai kemahiran dalam mereka cipta produk yang boleh dikomersialkan. Hasil dapatan kajian membuktikan bahawa pelajar-pelajar ini berminat dalam bidang keusahawanan namun masih kurang pengetahuan tentang pengurusan modal terutamanya dalam menentukan modal permulaan, pengurusan modal keija dan caracara menentukan pembiayaan kewangan menggunakan kaedah jualan harian. Oleh itu, satu garis panduan Pengurusan Modal dibina untuk memberi pendedahan kepada mereka

Efficient reconfigurable architectures for 3D medical image compression

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.Ministry of Higher Education Malaysia (MOHE), Universiti Tun Hussein Onn Malaysia (UTHM) and the British Counci

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

International audienceIn this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MARTE that abstracts the technologic aspects of the chosen back-end. The so- obtained UML platform is transformed in an IP-XACT design, which is exploited to generate the files used by XPS for system implementation. In this way, we promote IP reuse and deployment while remaining back-end independent, by using specific vendor extensions. Finally, we analyze the advantages of the proposed methodology by a case study in system integration

RTRLIB : a high-level modeling tool for dynamically partially reconfigurable systems

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2020.Reconfiguração dinâmica parcial é considerada uma interessante técnica a ser aplicada para o aumento da flexibilidade de sistemas implementados em FPGA, em função da implementação dinâmica de módulos de hardware enquanto o restante do circuito permanece em operação. Trata- se de uma técnica utilizada em sistemas com requisitos muito restritos, como adaptabilidade, robustez, consumo de potência, custo e tolerância à falhas. Entretanto, a complexidade de desen- volvimento de sistemas com reconfiguração dinâmica parcial é consideravelmente alta quando comparada à de sistemas com lógica totalmente estática. Nesse sentido, novas metodologias e ferramentas de desenvolvimento são necessárias para reduzir a complexidade de implementação desse tipo de sistema. Nesse contexto, esse trabalho apresenta o RTRLib, uma ferramenta de modelagem em alto nível para o desenvolvimento de sistemas com reconfiguração dinâmica parcial em dispositivos Xilinx Zynq a partir da especificação e parametrização de alguns blocos. Sob condições específi- cas, o RTRLib automaticamante produz os scripts de hardware e software para implementação da solução utilizando o Vivado Design Suite e o SDK. Tais scripts são compostos pelos comandos necessários para a implementação do sistema desde a criação do projeto de hardware até a criação do arquivo de boot. Uma vez que o RTRLib é composto por IP-Cores previamente caracterizados, a ferramenta também pode ser utilizada para a análise, em fase de modelagem, do sistema a ser implementado, por meio da estimação de características importantes do sistema, como o consumo de recursos e latência. O presente trabalho também inclui novas funcionalidades implementadas no RTRLib no con- texto do design de hardware e de software, como: generalização do script de hardware, mapea- mento de IO, floorplanning por meio de uma GUI, criação de um gerador de script de software, gerador de template de aplicação standalone que faz uso do partial reconfiguration controller (PRC) e implementação de uma biblioteca para aplicações FreeRTOS. Por fim, quatro estudos de casos foram implementados para demonstrar as funcionalidades da ferramenta: um sistema de classificação de terrenos baseado em redes neurais, um sistema com regressores lineares utilizado para controle de uma prótese miocinética de mão e, por último, uma aplicação hipotética de um sistema com requisitos de tempo real.Partial dynamic reconfiguration is considered an interesting technique to increase flexibility in FPGA designs due to the dynamic replacement of hardware modules while the remainder of the circuit remains in operation. It is used in systems with hard requirements such as adaptability, robustness, power consumption, cost, and fault-tolerance. However, the complexity to develop dynamically partially reconfigurable systems in considerably higher comparing with static de- signs. Therefore, new design methodologies and tools have been required to reduce the design complexity of such systems. In this context, this work presents the RTRLib, a high-level modeling tool for the development of dynamically reconfigurable systems on Xilinx Zynq devices by a simple system specification and parametrization of some blocks. Under specific conditions, RTRLib automatically generates the hardware and software scripts to implement the solution using Vivado and SDK. These scripts are composed by the sequential design steps from hardware project creation to the boot image elaboration. Since RTRLib is composed of pre-characterized IP-Cores, the tool also can be used to analyze the system behavior during the design process by the early estimation of essential characteristics of the system such as resource consumption and latency. The present work also includes the new functionalities implemented on RTRLib in the context of the hardware and the software design, such as: hardware script generalization, IO mapping, floorplanning by a GUI, software script creation, generator of a standalone template application that uses PRC, and implementation of a FreeRTOS library application. Finally, four case studies were implemented to demonstrate the tool capability: a system for terrain classification based on neuron networks, a linear regressor system used to control a myokinetic-based prosthetic hand, and a hypothetical real-time application

Information security frameworks assisting GDPR compliance in bank industry

In the last years, with the consequent increase use of Information Technology (IT) by the population, we watched an increase in the collection and processing of data by the organizations, for various purposes, such as for example the necessary provision of services or marketing campaigns. As a result of the increase of data, there have been several attempts to steal the data to sell or request redemptions from organizations. This situation has shown that organizations as regards data protection and security do not all have the same degree of maturity, and a determining aspect is also that the existing legislation is not the most adequate for the level of IT use in the days of today. To address these issues, the European Union (EU) decided to create the General Data Protection Regulation (GDPR), which entered into force on May 25, 2018, applicable to all organizations dealing with personal data of citizens residing in the European Union. In effect, the organizations combine all their efforts for the implementation of this new regulation, so that fines for non-compliance are not applied. Based on the previous description and with base on a set of best practices and existing frameworks of information security existent currently in the market, this thesis aims to explore how can current IS frameworks help Banks comply with GDPR by mapping the requirements of the regulation with the practices of the frameworks. In a second phase, interviews will be conducted with professionals in the field, in a specific sector where there is more sensitivity for these topics, the bank industry.Nos últimos anos com o consequente aumento do uso de Tecnologias de Informação (TI) pela população, assistimos a um aumento da recolha e tratamento dos dados por parte das organizações, destinando-se a diversos fins, como por exemplo, para a necessária prestação de serviços ou campanhas de marketing. Como consequência do aumento de dados, têm existido diversas tentativas de roubo dos mesmos para se vender ou pedir resgates às organizações. Esta situação tem revelado que as organizações no que respeita à segurança e proteção de dados nem todas têm o mesmo grau de maturidade, sendo que um aspeto também determinante é a legislação existente não ser a mais adequada para o nível de utilização das TI nos dias de hoje. Para colmatar estas falhas a União Europeia (UE) decidiu criar o Regulamento Geral de Proteção de Dados (RGPD), com entrada em vigor a 25 de maio de 2018, aplicável a todos as organizações que tratam dados pessoais de cidadãos residentes na União Europeia (EU). Com efeito as organizações conjugam todos os seus esforços para a implementação deste novo regulamento, de forma a que não sejam aplicadas multas por incumprimento ao mesmo. À imagem do que foi descrito anteriormente e com base num conjunto de boas práticas e frameworks existentes sobre segurança da informação atualmente no mercado, esta tese propõe explorar como os frameworks de segurança da informação podem ajudar os bancos a cumprir com o RGPD, através do mapeamento dos requisitos do regulamento com as práticas dos frameworks. Numa segunda fase realizar-se-á entrevistas com responsáveis na matéria, num setor específico onde existe mais sensibilidade no que toca a estes temas, o setor da banca

Co-regulating the Indonesian Digital Economy

Executive Summary The Gross Merchandise Value of the Indonesian digital economy has been growing at an annual rate of over 40% since 2015 and is predicted to reach USD 130 billion by 2025. This makes Indonesia the most promising digital market among its geographic neighbors. To facilitate further growth of the digital economy, the government must ensure the safety of the digital ecosystem for its users while providing an environment conducive to innovation. The government should pursue these goals by focusing on four policy areas: consumer protection, data privacy, cybersecurity, and e-payments. These areas are important due to the existence of regulatory deficiencies that if resolved, would accelerate the inclusive development of Indonesia’s digital economy. Although they are treated separately, at times these areas overlap and impact the nation’s digital economy environment. The existing consumer protection regulatory framework cannot accommodate emerging business models and instead imposes potential barriers to doing business; for example, in the form of licensing requirements for online sellers. Increasingly frequent data breaches and cyberattacks have highlighted the importance of data privacy and cybersecurity; yet here, too, the regulatory framework is incomplete and important bills are still being deliberated. The regulatory framework of e-payments is more advanced. In this area, the Indonesian government has established a clear policy blueprint and more innovative regulatory approaches, including a regulatory sandbox. The central bank of Indonesia (BI) and the Indonesian government’s financial services industry regulator (OJK) maintain a continuous dialogue with businesses, which creates and maintains a regulatory environment conducive to innovation. However, problems with e-payments remain in the areas of cybersecurity and data privacy. To regulate these areas of the digital economy effectively, a process of co-regulation is required. Co-regulation is a regulatory approach that emphasizes responsibility-sharing between state and non-state actors such as broad-based private sector stakeholders in policymaking and enforcement. It focuses on collaboration in the creation, adoption, enforcement, and evolution of policies and regulations. It is helpful for regulating the digital economy because it may provide the state with necessary data and knowledge, a mechanism for dialogue and flexible adaptation of legislative solutions in the new and fast-changing digital economy, and facilitate regulatory enforcement. To implement co-regulation, a Public-Private Dialogue (PPD) process needs to be established. The PPD needs to include the key stakeholders, such as government officials, business associations, civil society organizations, academia, and provide sufficient time for the process. Government actors should consider digital tools for collecting public input and to allow businesses to submit a regulatory impact assessment during a regulation’s lifetime. A formal process for sharing responsibility between public and private sectors must also be established. Involving businesses in the regulatory process, for example when testing new policies, helps ensure regulations remain enforceable without stifling innovative processes. The flexibility of this process allows regulators to accommodate the rapid changes of digital technology. A regulatory sandbox is a practical and positive example of such a process. It provides a policy innovation space for policymakers and businesses to engage in ideation, iteration, and experimentation within temporary, flexible regulatory, or legal frameworks. Finally, a monitoring and evaluation mechanism is needed to periodically review the co-regulation process and ensure that all lessons learned are on-the-record and transparent. This paper is divided into four sections. Section one highlights the landscape of the Indonesian digital economy, section two describes approaches in regulating the digital economy, and section three explores regulatory challenges. In the end, the paper presents ways to improve the regulatory framework of Indonesia’s digital economy

Redocumentation through design pattern recovery:: an investigation and an implementation

In this thesis, two methods are developed in an aid to help users capture valuable design information and knowledge and reuse them. They are the design pattern recovery (DPR) method and pattern-based redocumentation (PBR) method. The DPR method is for matching up metrics of patterns with patterns themselves in order to capture valuable design information. Patterns are used as a container for storing the information. Two new metrics, i.e., p-value and s-value are introduced. They are obtained by analysing product metrics statistically. Once patterns have been detected from a system, the system can be redocumented using these patterns. Some existing XML (extensible Markup Language) technologies are utilised in order to realise the PRB method. Next, a case study is carried out to validate the soundness and usefulness of the DPR method. Finally, some conclusions drawn from this research are summarised, and further work is suggested for the researchers in software engineering

Reconfigurable Computing Systems for Robotics using a Component-Oriented Approach

Robotic platforms are becoming more complex due to the wide range of modern applications, including multiple heterogeneous sensors and actuators. In order to comply with real-time and power-consumption constraints, these systems need to process a large amount of heterogeneous data from multiple sensors and take action (via actuators), which represents a problem as the resources of these systems have limitations in memory storage, bandwidth, and computational power. Field Programmable Gate Arrays (FPGAs) are programmable logic devices that offer high-speed parallel processing. FPGAs are particularly well-suited for applications that require real-time processing, high bandwidth, and low latency. One of the fundamental advantages of FPGAs is their flexibility in designing hardware tailored to specific needs, making them adaptable to a wide range of applications. They can be programmed to pre-process data close to sensors, which reduces the amount of data that needs to be transferred to other computing resources, improving overall system efficiency. Additionally, the reprogrammability of FPGAs enables them to be repurposed for different applications, providing a cost-effective solution that needs to adapt quickly to changing demands. FPGAs' performance per watt is close to that of Application-Specific Integrated Circuits (ASICs), with the added advantage of being reprogrammable. Despite all the advantages of FPGAs (e.g., energy efficiency, computing capabilities), the robotics community has not fully included them so far as part of their systems for several reasons. First, designing FPGA-based solutions requires hardware knowledge and longer development times as their programmability is more challenging than Central Processing Units (CPUs) or Graphics Processing Units (GPUs). Second, porting a robotics application (or parts of it) from software to an accelerator requires adequate interfaces between software and FPGAs. Third, the robotics workflow is already complex on its own, combining several fields such as mechanics, electronics, and software. There have been partial contributions in the state-of-the-art for FPGAs as part of robotics systems. However, a study of FPGAs as a whole for robotics systems is missing in the literature, which is the primary goal of this dissertation. Three main objectives have been established to accomplish this. (1) Define all components required for an FPGAs-based system for robotics applications as a whole. (2) Establish how all the defined components are related. (3) With the help of Model-Driven Engineering (MDE) techniques, generate these components, deploy them, and integrate them into existing solutions. The component-oriented approach proposed in this dissertation provides a proper solution for designing and implementing FPGA-based designs for robotics applications. The modular architecture, the tool 'FPGA Interfaces for Robotics Middlewares' (FIRM), and the toolchain 'FPGA Architectures for Robotics' (FAR) provide a set of tools and a comprehensive design process that enables the development of complex FPGA-based designs more straightforwardly and efficiently. The component-oriented approach contributed to the state-of-the-art in FPGA-based designs significantly for robotics applications and helps to promote their wider adoption and use by specialists with little FPGA knowledge

Privacy-preserving collaboration in an integrated social environment

Privacy and security of data have been a critical concern at the state, organization and individual levels since times immemorial. New and innovative methods for data storage, retrieval and analysis have given rise to greater challenges on these fronts. Online social networks (OSNs) are at the forefront of individual privacy concerns due to their ubiquity, popularity and possession of a large collection of users' personal data. These OSNs use recommender systems along with their integration partners (IPs) for offering an enriching user experience and growth. However, the recommender systems provided by these OSNs inadvertently leak private user information. In this work, we develop solutions targeted at addressing existing, real-world privacy issues for recommender systems that are deployed across multiple OSNs. Specifically, we identify the various ways through which privacy leaks can occur in a friend recommendation system (FRS), and propose a comprehensive solution that integrates both Differential Privacy and Secure Multi-Party Computation (MPC) to provide a holistic privacy guarantee. We model a privacy-preserving similarity computation framework and library named Lucene-P2. It includes the efficient privacy-preserving Latent Semantic Indexing (LSI) extension. OSNs can use the Lucene-P2 framework to evaluate similarity scores for their private inputs without sharing them. Security proofs are provided under semi-honest and malicious adversary models. We analyze the computation and communication complexities of the protocols proposed and empirically test them on real-world datasets. These solutions provide functional efficiency and data utility for practical applications to an extent.Includes bibliographical references