Design and modeling of integrated octagonal shape inductor with substrate silicon in a buck converter

The paper discusses the design and modeling of an integrate octagonal shaped inductor with silicon substrate. A validated equivalent electrical model of the integrated octagonal shaped spiral inductor is developed. The model is used to analyze and evaluate the quality factor and the inductance of the inductor structure proposed under different physical parameters setting. These include the number of turns, spacing between turns and the inner diameter. The simulation results show that an appropriate selection of physic a parameters can achieve an enhanced quality factor and improved inductance. PSIM simulator is used for the implementation of the integrated inductor in a micro buck converter. The simulation results demonstrate that our proposals are very promising approaches for the monolithic integration of DC-DC converters

An Extremely Miniaturized Two-stage Bandpass

Bandpass filters are key components in RF/microwave communication systems. As the system goes smaller and lighter, size reduction becomes more and more important. In addition, impedance matching and high performance is also crucial to a communication system. Thus, a two-stage bandpass filter with both small size and automatically matching is more desirable. In this thesis, a novel miniaturized CMOS bandpass filter will be introduced. It is based on the structure of diagonally short-ended coupled line with loaded capacitors for size reduction and using multilayer conductors for high quality factor. In this structure, the ground plane is capsulated around the filter, which enables it avoid the coupling to other basic components in the transceiver system. In addition, as another major advantage, it was proven to have an impedance matching automatically. The greater difference between the simulation and measurement in CMOS fabrication is also analysed and it will be proven to be caused by transmission losses and quality factors in the lossy distributed inductor of shunt resonator. Design equations and method will be fully explained in this thesis. A lot of simulated results and measured results are also presented. The method of enhancing the performance of the bandpass filters and automatically impedance matching will be described. Four kinds of circuits which based on the MagnaChip 0.18μm process are fabricated. Many simulated and measured data are collected and provided here to show the advantages of the proposed bandpass filter.Contents Nomenclature List of Figures Abstract CHAPTER 1 Introduction 1.1 An introduction to the filters at present 1.2 Organization of the thesis CHAPTER 2 The Bandpass Filter Design Theory 2.1 Size reduction method 2.2 The two-stage filter 2.3 The inter-stage signal line enhancement method CHAPTER 3 The Simulation , fabrication and results analysis 3.1 The inter-stage signal line improvement 3.2 Simulation and fabrication 3.3 The quality factor effect on the resonance frequency shift CHAPTER 4 Conclusion References Acknowledgemen

A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier

A 2.4-GHz, 2.2-W, 2-V fully integrated circular geometry power amplifier with 50 Ω input and output matching is fabricated using 2.5V, 0.35 pm CMOS transistors. It can also produce 450mW using a 1V supply. Harmonic suppression is 64dB or better. An on-chip circular-geometry active-transformer is used to combine several push-pull low-voltage amplifiers efficiently to produce a larger output power while maintaining a 50 Ω match. This new on-chip power combining and impedance matching method uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component such as wirebonds. It also desensitizes the operation of the amplifier to the inductance of bonding wires and makes the design more reproducible. This new topology makes possible a fully-integrated 2.2W, 2.4GHz, low voltage CMOS power amplifier for the first time

On-chip Spiral Inductor/transformer Design And Modeling For Rf Applications

Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC\u27s such as low-noise amplifiers and oscillators. High performance inductor has become one of the critical components for voltage controlled oscillator (VCO) design, for its quality factor (Q) value directly affects the VCO phase noise. The optimization of inductor layout can improve its performance, but the improvement is limited by selected technology. Inductor performance is bounded by the thin routing metal and small distance from lossy substrate. On the other hand, the in-accurate inductor modeling further limits the optimization process. The on-chip inductor has been an important research topic since it was first proposed in early 1990\u27s. Significant amount of study has been accomplished and reported in literature; whereas some methods have been used in industry, but not released to public. It is of no doubt that a comprehensive solution is not exist yet. A comprehensive study of previous will be first address. Later author will point out the in-adequacy of skin effect and proximity effect as cause of current crowding in the inductor metal. A model method embedded with new explanation of current crowding is proposed and its applicability in differential inductor and balun is validated. This study leads to a robust optimization routine to improve inductor performance without any addition technology cost and development

Optimal design of a 2.4 GHz CMOS low noise amplifier

In most RF receivers, the Low Noise Amplifier (LNA) is normally the first component, whose performance is very critical. For the LNA architecture that uses source degeneration inductors and cascode topology, the performance depends largely on the performance of the inductors. All the parasitics associated with the inductors should be thoroughly analyzed and taken into consideration while designing the LNA. The work presented in this thesis can be broadly classified as follows: optimization of the LNA design with respect to all the parasitics associated with the on-chip spiral inductors, modeling high performance inductors, which are embedded in the silicon substrate and analysis of parasitic effects from the Electro Static Discharge (ESD) protection circuitry on the performance of the LNA. A methodology has been developed such that the LNA design can be optimized in the presence of an ESD protection circuitry in order to achieve the required input impedance match. This optimization procedure is presented for all possible placements of the ESD protection circuitry at the input of the LNA, that is, with respect to the gate inductor being realized on-chip or off-chip or a combination of on-chip and off-chip inductors. The thesis presents the procedure to vary the source inductance and gate inductance values in the presence of parasitic ESD capacitance in order to optimize LNA design such that the required input impedance match is maintained