High level synthesis of RDF queries for graph analytics

In this paper we present a set of techniques that enable the synthesis of efficient custom accelerators for memory intensive, irregular applications. To address the challenges of irregular applications (large memory footprint, unpredictable fine-grained data accesses, and high synchronization intensity), and exploit their opportunities (thread level parallelism, memory level parallelism), we propose a novel accelerator design that employs an adaptive and Distributed Controller (DC) architecture, and a Memory Interface Controller (MIC) that supports concurrent and atomic memory operations on a multi-ported/multi-banked shared memory. Among the multitude of algorithms that may benefit from our solution, we focus on the acceleration of graph analytics applications and, in particular, on the synthesis of SPARQL queries on Resource Description Framework (RDF) databases. We achieve this objective by incorporating the synthesis techniques into Bambu, an Open Source high-level synthesis tools, and interfacing it with GEMS, the Graph database Engine for Multithreaded Systems. The GEMS' front-end generates optimized C implementations of the input queries, modeled as graph pattern matching algorithms, which are then automatically synthesized by Bambu. We validate our approach by synthesizing several SPARQL queries from the Lehigh University Benchmark (LUBM)

Design synthesis for dynamically reconfigurable logic systems

Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced reconfigurable logic design expert. This thesis proposes an automatic synthesis method which relieves designers of some of the difficulties associated with designing partially dynamically reconfigurable systems. A new design abstraction model for reconfigurable systems is proposed in order to support design exploration using the presented method. Given an input behavioural model, a technology server and a set of design constraints, the method will generate a reconfigurable design solution in the form of a 3D floorplan and a configuration schedule. The approach makes use of genetic algorithms. It facilitates global optimisation to accommodate multiple design objectives common in reconfigurable system design, while making realistic estimates of configuration overheads and of the potential for resource sharing between configurations. A set of custom evolutionary operators has been developed to cope with a multiple-objective search space. Furthermore, the application of a simulation technique verifying the lll results of such an automatic exploration is outlined in the thesis. The qualities of the proposed method are evaluated using a set of benchmark designs taking data from a real reconfigurable logic technology. Finally, some extensions to the proposed method and possible research directions are discussed

High-level synthesis of dataflow programs for heterogeneous platforms:design flow tools and design space exploration

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for complex systems, raising the level of abstraction does not necessarily come at a cost in terms of performance or resource requirements. As a matter of fact, high-level synthesis tools supporting such a high abstraction often rival and on occasion improve low-level design. In spite of these successes, high-level synthesis still relies on programs being written with the target and often the synthesis process, in mind. In other words, imperative languages such as C or C++, most used languages for high-level synthesis, are either modified or a constrained subset is used to make parallelism explicit. In addition, a proper behavioral description that permits the unification for hardware and software design is still an elusive goal for heterogeneous platforms. A promising behavioral description capable of expressing both sequential and parallel application is RVC-CAL. RVC-CAL is a dataflow programming language that permits design abstraction, modularity, and portability. The objective of this thesis is to provide a high-level synthesis solution for RVC-CAL dataflow programs and provide an RVC-CAL design flow for heterogeneous platforms. The main contributions of this thesis are: a high-level synthesis infrastructure that supports the full specification of RVC-CAL, an action selection strategy for supporting parallel read and writes of list of tokens in hardware synthesis, a dynamic fine-grain profiling for synthesized dataflow programs, an iterative design space exploration framework that permits the performance estimation, analysis, and optimization of heterogeneous platforms, and finally a clock gating strategy that reduces the dynamic power consumption. Experimental results on all stages of the provided design flow, demonstrate the capabilities of the tools for high-level synthesis, software hardware Co-Design, design space exploration, and power optimization for reconfigurable hardware. Consequently, this work proves the viability of complex systems design and implementation using dataflow programming, not only for system-level simulation but real heterogeneous implementations

Green Logistics : Advanced Methods for Transport Logistics Management Systems Including Platooning and Alternative Fuel Powered Vehicles

Green Logistics has attracted increased attention from researchers during the last few years, due to the growing environmental awareness. Road Transport is a major factor in climate change and accounts for a large proportion of the total UK emissions, including Carbon Dioxide (CO₂). With traffic and congestion levels growing, efficient routing combined with greener (more environmentally friendly) vehicles will be of great importance. The purpose of this thesis is two-fold: i) to provide an insight into Green Logistics and ways in which green technologies can be combined within the vehicle routing problem and ii) identifying new variants of the Vehicle Routing Problem (VRP) that can be applied to real-life instances; The Platooning Routing Problem with Changing Split Points, and the proposition of a Hyper-Realistic Electric Vehicle Energy Consumption model that can be applied to the E-VRP. A thorough CO₂ experiment was also conducted on a rolling road, providing useful data that future research can use to further increase the accuracy of routing models. The platooning of vehicles proves to be an important technique that can lead to large decreases in fuel consumption and can be easily implemented in most transport systems; the process requires advanced and accurate computer systems that are only now becoming available to manufacturers. The Platooning model is designed and tested within this thesis and it is hoped to spark further interest in this crucial area of research. Extensions to the Platooning Problem include the addition of heterogeneous fleets and how they change the dynamics of the proposed problems, as well as further work on the placement of the critical splitting point. Allowing the consideration of using limited range Electric Vehicles (EVs) as well as Conventional Vehicles (CVs) and Alternative Fuel powered Vehicles (AFVs) can further increase the emission savings and are becoming progressively popular in today's society. We therefore have carried out extensive research around the area of AFV's including detailed battery specifics for EV's. The objective is to minimise the amount of emissions while satisfying the time window requirements of customers maintaining low overall financial costs. The resulting emissions are largely affected by the electricity fuel mix of the country, we found that the indirect EV emissions for a 30kwh EV can vary by as much as 33% throughout the day and as much as 68% throughout the year with different seasons. Various heuristic and metaheuristic solution techniques as well as several classical heuristics are implemented including the Clarke and Wright Savings heuristic algorithm (CWSA), the Sweep Algorithm and the Variable Neighbourhood Search (VNS) method. These heuristic and metaheuristic models are tested on the Christofides et al. datasets and we achieve solutions that are on average 1.67% and 8.5% deviated from the best-known solution for unrestricted route lengths and restricted max route length problems respectively. Following this a platooning model is generated and tested on various datasets, including a real-life example along the roads of the South East of the UK. Platooning proves to bring benefits to the VRP, with the extensions discussed in this thesis providing increased savings to emissions. On three of the dataset problems of the small and medium size problems a significant fuel saving of more than 1% was achieved. With future research and additional avenues explored Platooning can make a significant reduction to emissions and make an impact on improving air quality. The EV model proposed is designed to trigger further research on ultra-realistic energy models with the aim of being applied to a real-life organisation with various constraints including factors such as battery health, travel speed, vehicle load and transportation distance. This thesis provides useful insights into how important the aspect of environmental route planning is, providing advice on tangible and intangible benefits such as cost savings and a reduction in carbon emissions

フロアプラン指向高位合成手法とイジング計算機応用に関する研究

早大学位記番号:新7790早稲田大

Power-aware through-silicon-via minimization by partitioning finite state machine with datapath

This paper proposes an extended Finite State Machine with Datapath (FSMD) partitioning that performs three-dimensional (3D) high level synthesis (HLS) with objectives to minimize the number of through-silicon-via (TSV) and to equip the synthesized system with power gating capability to save power. The original FSMD partitioning was proposed for conventional low-power 2D system and was only employed before HLS. Our extended FSMD partitioning problem is formulated using integer linear programming (ILP) to minimize TSVs under constraints of footprint area, power limit, number of die stacks and HLS rules. Case study has been conducted on Discrete Cosine Transform (DCT) circuit to evaluate the effectiveness of the proposed method in terms of number of TSVs and power dissipation. Besides, power gating capability is verified and analyzed