Precise Network Time Monitoring: Picosecond-level packet timestamping for Fintech networks

Network visibility and monitoring are critical in modern networks due to the increased density, additional complexity, higher bandwidth, and lower latency requirements. Precise packet timestamping and synchronization are essential to temporally correlate captured information in different datacenter locations. This is key for visibility, event ordering and latency measurements in segments as telecom, power grids and electronic trading in finance, where order execution and reduced latency are critical for successful business outcomes. This contribution presents Precise Network Time Monitoring (PNTM), a novel mechanism for asynchronous Ethernet packet timestamping which adapts a Digital Dual Mixer Time Difference (DDMTD) implemented in an FPGA. Picosecond-precision packet timestamping is outlined for 1 Gigabit Ethernet. Furthermore, this approach is combined with the White Rabbit (WR) synchronization protocol, used as reference for the IEEE 1588-2019 High Accuracy Profile to provide unprecedented packet capturing correlation accuracy in distributed network scenarios thanks to its sub-nanosecond time transfer. The paper presents different application examples, describes the method of implementation, integration of WR with PNTM and subsequently describes experiments to demonstrate that PNTM is a suitable picosecond-level distributed packet timestamping solutionNational project AMIGA7 RTI2018-096228-B-C32Andalusian project SINPA B-TIC-445-UGR1

System-on-chip architecture for secure sub-microsecond synchronization systems

213 p.En esta tesis, se pretende abordar los problemas que conlleva la protección cibernética del Precision Time Protocol (PTP). Éste es uno de los protocolos de comunicación más sensibles de entre los considerados por los organismos de estandarización para su aplicación en las futuras Smart Grids o redes eléctricas inteligentes. PTP tiene como misión distribuir una referencia de tiempo desde un dispositivo maestro al resto de dispositivos esclavos, situados dentro de una misma red, de forma muy precisa. El protocolo es altamente vulnerable, ya que introduciendo tan sólo un error de tiempo de un microsegundo, pueden causarse graves problemas en las funciones de protección del equipamiento eléctrico, o incluso detener su funcionamiento. Para ello, se propone una nueva arquitectura System-on-Chip basada en dispositivos reconfigurables, con el objetivo de integrar el protocolo PTP y el conocido estándar de seguridad MACsec para redes Ethernet. La flexibilidad que los modernos dispositivos reconfigurables proporcionan, ha sido aprovechada para el diseño de una arquitectura en la que coexisten procesamiento hardware y software. Los resultados experimentales avalan la viabilidad de utilizar MACsec para proteger la sincronización en entornos industriales, sin degradar la precisión del protocolo

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Scalable System Design for Covert MIMO Communications

In modern communication systems, bandwidth is a limited commodity. Bandwidth efficient systems are needed to meet the demands of the ever-increasing amount of data that users share. Of particular interest is the U.S. Military, where high-resolution pictures and video are used and shared. In these environments, covert communications are necessary while still providing high data rates. The promise of multi-antenna systems providing higher data rates has been shown on a small scale, but limitations in hardware prevent large systems from being implemented

IEEE 1588 High Accuracy Default Profile: Applications and Challenges

Highly accurate synchronization has become a major requirement because of the rise of distributed applications, regulatory requests and position, navigation and timing backup needs. This fact has led to the development of new technologies which fulfill the new requirements in terms of accuracy and dependability. Nevertheless, some of these novel proposals have lacked determinism, robustness, interoperability, deployability, scalability or management tools preventing them to be extensively used in real industrial scenarios. Different segments require accurate timing information over a large number of nodes. Due to the high availability and low price of global satellite-based time references, many critical distributed facilities depend on them. However, the vulnerability to jamming or spoofing represents a well-known threat and back-up systems need to be deployed to mitigate it. The recently approved draft standard IEEE 1588-2019 includes the High Accuracy Default Precision Time Protocol Profile which is intensively based on the White Rabbit protocol. White Rabbit is an extension of current IEEE 1588-2008 network synchronization protocol for sub-nanosecond synchronization. This approach has been validated and intensively used during the last years. This paper revises the pre-standard protocol to expose the challenges that the High Accuracy profile will find after its release and covers existing applications, promising deployments and the technological roadmap, providing hints and an overview of features to be studied. The authors review different issues that have prevented the industrial adoption of White Rabbit in the past and introduce the latest developments that will facilitate the next IEEE 1588 High Accuracy extensive adoption.This work was supported in part by the AMIGA6 under Grant AYA2015-65973-C3-2-R, in part by the AMIGA7 under Grant RTI2018-096228-B-C32, and in part by the Torres Quevedo under Grant PTQ2018-010198

On the Exploration of FPGAs and High-Level Synthesis Capabilities on Multi-Gigabit-per-Second Networks

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid, Escuela Politécnica Superior, Departamento de Tecnología Electrónica y de las Comunicaciones. Fecha de lectura: 24-01-2020Traffic on computer networks has faced an exponential grown in recent years. Both links and communication equipment had to adapt in order to provide a minimum quality of service required for current needs. However, in recent years, a few factors have prevented commercial off-the-shelf hardware from being able to keep pace with this growth rate, consequently, some software tools are struggling to fulfill their tasks, especially at speeds higher than 10 Gbit/s. For this reason, Field Programmable Gate Arrays (FPGAs) have arisen as an alternative to address the most demanding tasks without the need to design an application specific integrated circuit, this is in part to their flexibility and programmability in the field. Needless to say, developing for FPGAs is well-known to be complex. Therefore, in this thesis we tackle the use of FPGAs and High-Level Synthesis (HLS) languages in the context of computer networks. We focus on the use of FPGA both in computer network monitoring application and reliable data transmission at very high-speed. On the other hand, we intend to shed light on the use of high level synthesis languages and boost FPGA applicability in the context of computer networks so as to reduce development time and design complexity. In the first part of the thesis, devoted to computer network monitoring. We take advantage of the FPGA determinism in order to implement active monitoring probes, which consist on sending a train of packets which is later used to obtain network parameters. In this case, the determinism is key to reduce the uncertainty of the measurements. The results of our experiments show that the FPGA implementations are much more accurate and more precise than the software counterpart. At the same time, the FPGA implementation is scalable in terms of network speed — 1, 10 and 100 Gbit/s. In the context of passive monitoring, we leverage the FPGA architecture to implement algorithms able to thin cyphered traffic as well as removing duplicate packets. These two algorithms straightforward in principle, but very useful to help traditional network analysis tools to cope with their task at higher network speeds. On one hand, processing cyphered traffic bring little benefits, on the other hand, processing duplicate traffic impacts negatively in the performance of the software tools. In the second part of the thesis, devoted to the TCP/IP stack. We explore the current limitations of reliable data transmission using standard software at very high-speed. Nowadays, the network is becoming an important bottleneck to fulfill current needs, in particular in data centers. What is more, in recent years the deployment of 100 Gbit/s network links has started. Consequently, there has been an increase scrutiny of how networking functionality is deployed, furthermore, a wide range of approaches are currently being explored to increase the efficiency of networks and tailor its functionality to the actual needs of the application at hand. FPGAs arise as the perfect alternative to deal with this problem. For this reason, in this thesis we develop Limago an FPGA-based open-source implementation of a TCP/IP stack operating at 100 Gbit/s for Xilinx’s FPGAs. Limago not only provides an unprecedented throughput, but also, provides a tiny latency when compared to the software implementations, at least fifteen times. Limago is a key contribution in some of the hottest topic at the moment, for instance, network-attached FPGA and in-network data processing