A general framework for efficient FPGA implementation of matrix product

Original article can be found at: http://www.medjcn.com/ Copyright Softmotor LimitedHigh performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.Peer reviewe

Implementation of JPEG compression and motion estimation on FPGA hardware

A hardware implementation of JPEG allows for real-time compression in data intensivve applications, such as high speed scanning, medical imaging and satellite image transmission. Implementation options include dedicated DSP or media processors, FPGA boards, and ASICs. Factors that affect the choice of platform selection involve cost, speed, memory, size, power consumption, and case of reconfiguration. The proposed hardware solution is based on a Very high speed integrated circuit Hardware Description Language (VHDL) implememtation of the codec with prefered realization using an FPGA board due to speed, cost and flexibility factors; The VHDL language is commonly used to model hardware impletations from a top down perspective. The VHDL code may be simulated to correct mistakes and subsequently synthesized into hardware using a synthesis tool, such as the xilinx ise suite. The same VHDL code may be synthesized into a number of sifferent hardware architetcures based on constraints given. For example speed was the major constraint when synthesizing the pipeline of jpeg encoding and decoding, while chip area and power consumption were primary constraints when synthesizing the on-die memory because of large area. Thus, there is a trade off between area and speed in logic synthesis

High volume colour image processing with massively parallel embedded processors

Currently Oc´e uses FPGA technology for implementing colour image processing for their high volume colour printers. Although FPGA technology provides enough performance it, however, has a rather tedious development process. This paper describes the research conducted on an alternative implementation technology: software defined massively parallel processing. It is shown that this technology not only leads to a reduction in development time but also adds flexibility to the design

Reconfigurable hardware for color space conversion

Color space conversion (CSC) is an important application in image and video processing systems. CSC has been implemented in software and various kinds of hardware. Hardware implementations can achieve a higher performance compared to software-only solutions. Application specific integrated circuits (ASICs) are efficient and have good performance. However, they lack the programmability of devices such as field programmable gate arrays (FPGAs). This thesis studies the performance vs. flexibility tradeoffs in the migration of an existing CSC design from an ASIC to an FPGA. The existing ASIC is used within a commercial color-printing pipeline. Performance is critical in this application. However, the flexibility of FPGAs is desirable for faster time to market and also the ability to reuse one physical device across multiple functions. This thesis investigates whether the reprogrammability of FPGAs can be used to reallocate idle resources and studies the suitability of FPGAs for image processing applications. In the ASIC design, two major conversion units that are never used at the same time are identified. The FPGA-based implementation instantiates only one of these two units at a time, thus saving area. Reconfiguring the FPGA switches which of the two units is instantiated. The goal is to configure the device and process an entire page within one second. The FPGA implementation is approximately a factor of three slower than the ASIC design, but fast enough to process one page per second. In the current setup, the configuration time is very high. It exceeds the total time allotted for both configuration and processing. However, other methods of configuration seem promising to reduce the time. Evaluation of the performance of the implementation and the reconfiguration time is presented. Methods to improve the performance and reduce the time and area for reconfiguration are discussed

Implementación en FPGA de un conversor de señal de video compuesto a señal VGA

This paper describes the design and implementation of a system for converting composite video signal to VGA signal, which performs the capture and display of video based on the ITU-R BT.601 standard for digital television monitors. The system has three main components: an analog sensor that delivers the composite digital video signal, a graphics card that converts analog video to digital in 4:2:2 sampling format and uses the color space YCbCr and finally a FPGA (NEXIS card 2 , with the integrated circuit 3s1200efg320 -5) where the design has been implemented for processing the video signal to be displayed on a monitor. In the FPGA have been developed 4:2:2 to 4:4:4 sampling conversion modules and the conversion module between YCbCr color space to RGB (color format used in display devices). The synthesis of the FPGA design has been made using the XST (Xilinx Synthesis Tool) that is part of the interface development ISE Project Navigator 13.3 of the Xilinx® company. The equations for the transformation between color spaces have been implemented and simulated in MATLAB ® for validation of results.En este artículo se presenta el diseño e implementación de un sistema de conversión de señal de video compuesto a señal VGA, el cual realiza la captura y despliegue de video basado en el estándar ITU-R BT.601 para monitores de televisión digital. El sistema cuenta con tres principales componentes: un sensor de video analógico que entrega la señal de video digital compuesta, una tarjeta digitalizadora que realiza la conversión del video analógico al digital en el formato de muestreo 4:2:2 y emplea el espacio de color YCbCr y finalmente un FPGA (tarjeta NEXIS 2, con el circuito integrado 3s1200efg320-5) en donde se ha implementado el diseño del procesamiento de la señal de video para poder ser desplegadas en un monitor. En el FPGA se han desarrollado los módulos de conversión de muestreo 4:2:2 al 4:4:4 y el módulo de conversión entre los espacios de color YCbCr al RGB (formato de color utilizado en los dispositivos de despliegue).  La síntesis del diseño en el FPGA se ha realizado utilizando la herramienta XST (Xilinx Synthesis Tool) que es parte de la interfaz de desarrollo ISE Project Navigator 13.3 de la compañía Xilinx®. Las ecuaciones para realizar la transformación entre los espacios de color han sido implementadas y simuladas en MATLAB® para la validación de resultados

Multi-Granular Optical Cross-Connect: Design, Analysis, and Demonstration

A fundamental issue in all-optical switching is to offer efficient and cost-effective transport services for a wide range of bandwidth granularities. This paper presents multi-granular optical cross-connect (MG-OXC) architectures that combine slow (ms regime) and fast (ns regime) switch elements, in order to support optical circuit switching (OCS), optical burst switching (OBS), and even optical packet switching (OPS). The MG-OXC architectures are designed to provide a cost-effective approach, while offering the flexibility and reconfigurability to deal with dynamic requirements of different applications. All proposed MG-OXC designs are analyzed and compared in terms of dimensionality, flexibility/reconfigurability, and scalability. Furthermore, node level simulations are conducted to evaluate the performance of MG-OXCs under different traffic regimes. Finally, the feasibility of the proposed architectures is demonstrated on an application-aware, multi-bit-rate (10 and 40 Gbps), end-to-end OBS testbed

The effects of destination image and perceived risk on revisit intention: a study in the south eastern coast of Sabah, Malaysia

This study investigated the effects of destination image and perceived risk on revisit intention in the South Eastern Coast of Sabah, Malaysia. A total of 171 questionnaires were collected from international tourists through a self-administered questionnaire. The result of this study identified that three dimensions of destination image (travel environment, natural attraction, entertainment, and events) had significant effects on revisit intention. However, perceived risk was not important to the tourists’ revisit intention. The findings have implications on the tourism industry, especially for key players such as the tourism board and travel companies. It also serves as a reference to destinations with a similar risk background